Software expands scope of FPGA prototyping

Altium is using Verific Design Automation's HDL Component Software in Nexar, the industry's first comprehensive, vendor-independent solution for embedded system-level design on an FPGA platform.

Altium is using Verific Design Automation's HDL Component Software in Nexar, the industry's first comprehensive, vendor-independent solution for embedded system-level design on an FPGA platform.

Verific's HDL Component Software includes C++ source code-based parsers, analysers and elaborators for Verilog and VHDL that are tightly integrated with Nexar.

Altium recently announced the expansion of HDL capabilities of Nexar with the introduction of support for Verilog through a licence agreement with Verific to use its HDL Component Software.

Designers using Nexar now have complete freedom in the choice of capture language.

They can use any combination of block diagram, VHDL and Verilog to capture circuit hardware for FPGA implementation.

Using Nexar, designers require little or no experience using HDLs or register transfer level (RTL) source code in order to put systems onto an FPGA.

Instead, Nexar enables designers to use familiar, board-level design methodologies to interactively design and implement a complete embedded system inside an FPGA, making the potential of FPGA-based embedded systems design accessible to all engineers.

Says Nick Martin, Altium's founder and CEO: "We felt that it was crucial to provide strong support for Verilog within Nexar".

"Rather than developing our own parsers and analysers, we found that Verific's well-engineered and reliable HDL Component Software was the right fit for our needs".

"We can focus on other aspects of Nexar, and strengthen its position as the universal design system of choice for FPGA-based systems development".

"Altium is breaking new ground for embedding systems on FPGAs and it gives us great pleasure to be able to help make this happen", adds Michiel Ligthart, Verific'S Chief Operating Officer.

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