Functional checker intercepts SoC bugs early

BlackTie functional checker from Verplex Systems is the industry's first full-chip multi-million-gate-capacity tool to accelerate the verification of SoC designs.

BlackTie functional checker from Verplex Systems is the industry's first full-chip multi-million-gate-capacity tool to accelerate the verification of SoC designs.

BlackTie provides exhaustive verification early in the design cycle to find as many RTL problems as possible - as bugs are easier to fix upstream.

Users can formally check event or assertion monitors in their designs to find deeply embedded bugs, where integration-level test vectors may have little control or may not be sufficiently long enough to propagate errors to an observable output.

Despite its thoroughness, BlackTie still manages to achieve high speed and capacity.

In a recent customer engagement it verified over 300,000 functional properties of a 2.7 million gate design in slightly over 20min using a standard Unix workstation.

Other formal RTL design verification solutions on the market currently require the user to break the design into smaller blocks - of roughly 50,000 gates.

Unfortunately, this 'divide and conquer' strategy means the full system level integration is not fully verified.

BlackTie, on the other hand, can verify hundreds of blocks that size collectively, catching many of the functional problems caused by SoC level integration that are elusive to other verification methods.

An open source assertion monitor library, written entirely in industry standard VHDL, makes BlackTie as easy to use as simulation.

The library enables, for the first time, simulation and formal verification to operate seamlessly.

The same checks that are written for simulation can be verified using BlackTie and vice versa.

When verifying assertion monitors with BlackTie, however, the added advantages are that test vectors are not required, coverage is exhaustive and the diagnosis automatic.

The assertion monitor library used by BlackTie, and which can be used on any Verilog simulator, is in the public domain and can be downloaded at no charge from the Open Verification Library web site http://www.verificationlib.org.

In addition to being the industry's first full-chip, multi-million gate capacity tool, BlackTie also automates the checking of global, commonplace errors.

For instance, instead of requiring designers to manually place an event or assertion monitor onto every bus structure of a design to check for contention problems, BlackTie does this automatically.

Other automatic checks include: asynchronous clock domain crossings; dead-end states; conflicting values loaded to multi-port registers; simultaneous set and reset conditions; mutual exclusivity checks; tristates that are stuck in a particular state.

BlackTie is shipping today and supports Hewlett Packard, Sun Microsystems and Linux operating systems.

It is available at a single unit perpetual license price of $75,000.

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