Product category:
Design and Development Software
News Release from: Verplex Systems
Edited by the Electronicstalk Editorial
Team on 14 June 2001
Verplex seeks acceptance for OVL library
Verplex Systems has contributed its Open Verification Language (OVL) library to electronics industry standards organisation Accellera.
Verplex Systems has contributed its Open Verification Language (OVL) library to electronics industry standards organisation Accellera OVL provides seamless interoperability between simulation and formal verification, eliminating the learning curve and accelerating the acceptance of formal RTL design validation software
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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The library was designed using Verilog hardware description language (HDL) and works with any Verilog HDL-based or mixed-language simulator.
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"Simulation and formal verification are key technologies for today's designers", says C.
Michael Chang, president and chief executive officer of Verplex.
"Accellera is noted and well respected for its efforts in the standardisation arena.
I can't think of a better place for OVL to ensure it become an industry standard".
Additionally, Verplex said it would work co-operatively with Co-Design Automation, developer of the Superlog system design language.
The purpose will be to further enable the seamless interoperability of simulation and formal verification through the use of common, user-friendly open standards.
Areas of co-operation would include refining and extending capabilities of OVL and Superlog.
An added benefit of this co-operation will be the extension simulation and formal verification flows to levels of abstraction beyond the register transfer level (RTL) of design.
More specific details will be announced soon.
(In a separate announcement, Co-Design Automation has announced it has contributed Superlog to Accellera.).
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