Product category:
Design and Development Software
News Release from: Verplex Systems | Subject: Conformal Logic Equivalence Checker
Edited by the Electronicstalk Editorial
Team on 18 September 2001
Formal verification just got faster
Verplex Systems has announced its next generation Conformal Logic Equivalence Checker.
Verplex Systems has announced its next generation Conformal Logic Equivalence Checker The product name change reflects major enhancements made to Verplex's market leading equivalence checker to deliver twice the speed of its predecessor
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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Functional checker intercepts SoC bugs early
BlackTie functional checker from Verplex Systems is the industry's first full-chip multi-million-gate-capacity tool to accelerate the verification of SoC designs.
Verification for high-density FPGAs
Verplex Systems and Xilinx have launched one of the first formal verification environments specifically for the design of high-density FPGAs.
Conformal combines increased performance and capacity with ease of use for the rapid and more reliable formal verification of full-chip designs.
It compares register transfer level (RTL) code to flattened netlists for multi-million-gate designs in minutes or hours, setting new performance standards for formal verification.
However, the doubling of Verplex's equivalence checking capabilities is only one of the many new features associated with Conformal.
Further reading
Verification library supports VHDL
Verplex Systems has expanded its Open Verification Library (OVL) to include support for the VHSIC hardware description language (VHDL).
Verification gets physical with complete SoC flow
Verplex Systems has made significant changes to its products to extend its market into the physical domain.
Its new RTL compiler reduces the complexity of the overall verification process, and abstracts designs to a higher level for faster design comparisons.
Improved comparison solvers enable designs to be verified 2-10X faster.
Conformal has also further optimised the comparison of RTL to gate multipliers, making them 10-50X faster according to customer feedback.
It automatically abstracts complex multiplier structures from synthesis design libraries generated by Synopsys DesignWare and Cadence Design Systems Ambit Ware.
Vendor-specific multipliers from LSI Logic Corporation and Texas Instruments are now supported.
Full adders that are used within multipliers are automatically recognised, which helps to speed up the comparisons process.
The new Conformal also supports Verilog2000 signed operator and attributes to stay current with hardware description language (HDL) constructs.
Improved navigation techniques now allow users to view schematic representations of functional blocks with bussed data and control distinction.
This feature aids during debug and last-minute engineering change orders (ECOs), especially with large, complex designs.
Additional GUI features and enhanced TCL support expand its diagnostic capabilities.
Mapping algorithms have been improved to further enhance ease of use.
A new mixed-language mode operation is well suited for SoC design applications, as well as designing with IP written in VHDL or Verilog.
Moreover, applications with different design styles can use Conformal's advances in sequential capability for gated-clocks, pipeline retiming, state encoding and cloned registers.
The support of user defined primitives has been enhanced to enable users to verify complex state element requirements in their designs.
Conformal is also tightly integrated with Verplex's Spice to logic abstraction tool, Transformal Transistor Extractor, to verify RTL designs against their final LVS netlist.
This is critical because the transistor-level netlist is the golden reference for physical design tools and for customer-owned tooling flows.
Conformal Logic Equivalence Checker is available today and supports Hewlett Packard, Sun Microsystems and Linux operating systems platforms.
It is priced at $105,000 US.
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