Product category:
Design and Development Software
News Release from: Verplex Systems | Subject: Conformal Equivalence Checker and Xilinx ISE
Edited by the Electronicstalk Editorial
Team on 26 September 2001
Verification for high-density FPGAs
Verplex Systems and Xilinx have launched one of the first formal verification environments specifically for the design of high-density FPGAs.
Verplex Systems and Xilinx have launched one of the first formal verification environments specifically for the design of high-density FPGAs The design environment includes Verplex's Conformal Equivalence Checker and Xilinx's Integrated Software Environment (ISE) 4.1i
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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BlackTie functional checker from Verplex Systems is the industry's first full-chip multi-million-gate-capacity tool to accelerate the verification of SoC designs.
Formal verification just got faster
Verplex Systems has announced its next generation Conformal Logic Equivalence Checker.
In related news, Verplex has announced that its Conformal Equivalence Checker now supports Xilinx Virtex, Virtex II Platform FPGAs and the Spartan II device family.
Formal verification has become an important piece of an FPGA design environment as design density increases.
Equivalence checking, part of a formal verification methodology, automatically detects functional inconsistencies, providing a reliable way to ensure that the final design implementation does what the register transfer level (RTL) code specifies.
Together with Xilinx ISE, Conformal Equivalence Checker can provide equivalence checking at the RTL and gate level of the design flow to functionally verify designs at every checkpoint.
Conformal Equivalence Checker and Xilinx ISE provide fast runtimes and high capacity to handle large FPGA designs.
Users can adopt the formal verification methodology at any design stage from the RTL design level to the final transistor level design.
Both have easy-to-use interfaces that enable designers to use them with minimal training Software in the FPGA formal verification design flow support Hewlett Packard and Sun Microsystems operating systems.
Tools are priced at separately.
Conformal Equivalence Checker is priced at $105,000 US.
New seats of ISE will be available in September with pricing starting at $695.
A free, downloadable WebPACK version will be available later this quarter.
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