Verification library supports VHDL

Verplex Systems has expanded its Open Verification Library (OVL) to include support for the VHSIC hardware description language (VHDL).

Verplex Systems has expanded its Open Verification Library (OVL) to include support for the VHSIC hardware description language (VHDL).

The open-source library, originally designed for Verilog HDL-based designers, provides seamless interoperability between simulation and formal verification, eliminating the learning curve and accelerating the acceptance of formal design validation software.

The library was designed using VHDL and works with any VHDL-based or mixed-language simulator.

Verplex donated its Verilog HDL-based Open Verification Language (OVL) library in 2001 to Accellera, an electronics industry standards organisation, to promote its use and encourage the library's acceptance as an industry standard.

Plans for donating the VHDL version of OVL to Accellera for standardisation will be announced shortly.

Verplex's BlackTie functional checker, a high-capacity formal verification tool that accelerates the verification of SoC designs, currently offers full support for the Verilog HDL version of OVL.

BlackTie support for the VHDL version of OVL will be announced later in the year.

"Developing a VHDL version of OVL is an important step for the industry", affirms C Michael Chang, president and chief executive officer of Verplex.

"Due to the overwhelming success of OVL within the Verilog community, we have received many requests to produce a VHDL-based version.

The VHDL market is still substantial and should have equal access to the same verification methodology advancements now enjoyed by the Verilog community".

Designers use OVL to capture design intent to be checked using standard, off-the-shelf verification tools, including both simulation and formal verification.

Often referred to as assertions or monitors, OVL checks are an effective means for designers to find bugs deeply embedded in the design, where chip- or system-level test vectors may have little control or may not be sufficiently long enough to propagate errors to an observable output.

The verification library can be downloaded at no charge from www.verificationlib.org.

The site features a download area, submission area, full documentation and a discussion group.

Visitors to the site are encouraged to contribute their own customised monitors and enhance existing ones.

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