Product category:
Design and Development Software
News Release from: Verplex Systems
Edited by the Electronicstalk Editorial
Team on 09 May 2002
Verplex throws its hat into Accelera
ring
Verplex Systems has added its support for the formal property language selected by the Accellera Formal Verification Technical Committee.
Verplex Systems has added its support for the formal property language selected by the Accellera Formal Verification Technical Committee The language is the industry's first standard for formal properties and was chosen after careful deliberation by members of the Technical Committee, representing a wide variety of EDA companies and their customers
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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"Our goal is to add support of Accellera's new formal language standard to our current support of Accellera's Open Verification Library (OVL) in a future release of our BlackTie functional checker", notes Dr Andy Lin, Verplex's vice president of engineering.
"Designers find OVL ideal for capturing RT-level implementation properties while formal languages offer system architects the desired flexibility for capturing block-level interface constraints.
The combination of the two creates a powerful convergence in verification methodologies".
Further reading
Verification for high-density FPGAs
Verplex Systems and Xilinx have launched one of the first formal verification environments specifically for the design of high-density FPGAs.
Verification library supports VHDL
Verplex Systems has expanded its Open Verification Library (OVL) to include support for the VHSIC hardware description language (VHDL).
The creation of the language was an electronics industry collaboration aimed at enabling a new generation of verification tools, libraries and methodologies united around the single language.
Currently, multiple EDA vendors offer verification tools with proprietary and incompatible formal languages, meaning that properties must rewritten, and new languages learned, for different tools.
Widespread adoption of the Accellera language would mean a leap in productivity for EDA vendors and customers alike.
Vendors can focus their resources to develop tools for a single language, and customers can focus on using a common standard for developing property libraries that can be reused with tools from multiple vendors.
"The Accellera Formal Verification Technical Committee defined an open, transparent and fair process for selection of the new industry-standard formal property language", remarks Harry Foster, chairman of the Technical Committee and chief architect at Verplex.
"The language offers an opportunity to enable a huge leap in productivity in electronics design and verification.
It is critical that the electronics industry now rally around the language, and develop and demand tools based on it".
Mike O'Reilly, vice president of marketing for Cadence's Systems and Functional Verification division, commented as well.
"Cadence is pleased to see that Verplex is fully participating in support of the Accellera standardisation efforts, which will enable cooperation among EDA vendors in order to better solve the verification challenges that our customers face".
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