Product category:
Design and Development Software
News Release from: Verplex Systems | Subject: Conformal and Transformal
Edited by the Electronicstalk Editorial
Team on 17 May 2002
Verification gets physical with complete
SoC flow
Verplex Systems has made significant changes to its products to extend its market into the physical domain.
Verplex Systems has announced significant advances to its products intended to extend its market into the physical domain The latest Verplex products are aimed at users of next-generation physical design closure tools, customer owned tooling (COT) flows and advanced ASIC flows
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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Functional checker intercepts SoC bugs early
BlackTie functional checker from Verplex Systems is the industry's first full-chip multi-million-gate-capacity tool to accelerate the verification of SoC designs.
Formal verification just got faster
Verplex Systems has announced its next generation Conformal Logic Equivalence Checker.
The Conformal logic equivalence checker (LEC) and Transformal logic transistor extractor (LTX) now perform advanced verification on all logic blocks of complex SoCs from register transfer level (RTL) to final layout versus schematics (LVS) netlist comparisons.
These blocks include memory, compiled datapath, memory control, intellectual property (IP) cores, complex I/O and full-custom logic.
Enhancements and tighter coupling of Verplex products to the transistor level, enable next-generation design tool users to compare final LVS netlists to their RTL golden designs helping them achieve functional closure faster and with more confidence.
Further reading
Verification for high-density FPGAs
Verplex Systems and Xilinx have launched one of the first formal verification environments specifically for the design of high-density FPGAs.
Verification library supports VHDL
Verplex Systems has expanded its Open Verification Library (OVL) to include support for the VHSIC hardware description language (VHDL).
Educational site covers formal verification
Verplex Systems has launched an online educational website for designers and verification engineers.
Verplex calls this new product flow Conformal layout versus RTL (LVR).
Traditionally, formal verification could not reach the transistor level, missing errors caused by mistakes in the layout process, the translation from gates to transistors, transistor-level engineering change orders (ECOs), optimisations, or manual errors during full-custom design.
Memories, memory controllers, I/O pads, hard IP cores and custom logic - all composed of transistors - can collectively dominate the real estate on SoCs.
Their verification is required to achieve signoff of the design.
Physical design closure tools frequently optimise and aggressively change designs late in the design cycle.
Designs then proceed from the gate level through the LVS process to reach tapeout.
Through tighter coupling to the transistor level, Conformal LVR enables physical design closure tool users to compare final layouts to their RTL golden designs.
This ensures that the greatest number of design implementation bugs are found.
Physical design closure tools often optimise across hierarchical boundaries, making it more difficult for formal verification tools to correlate these designs.
Verplex has enhanced the flexibility of its algorithms to more easily cope with these boundary changes.
Verplex has also added support for complex arithmetic operators compiled from higher-level descriptions, a common practice in SoC design.
These have been difficult to verify using formal verification technology due to the logical complexity of those circuits.
Verplex has overcome this problem, using proprietary adaptive algorithms that increase in efficiency as the comparison progresses.
Promising a higher performance level as well, Verplex has improved its proof engines to increase speed and capacity when handling RTL designs.
In some specific customer blocks, this has boosted the proof process by as much as 5 to 10 times.
In addition to its technological engine advancements, the enhanced flow boasts better performance during graphical debug and extended support for the Verilog2001 standard.
"Verplex has always offered robust verification for supporting complex designs", notes Bob Smith, vice president of product marketing at Magma Design Automation.
"We frequently recommend Verplex to our customers as the most reliable, independent source for verification.
Its latest release further expands the diversity of support it offers for critical SOC components and designs".
The latest versions of Conformal LEC and Transformal LTX are shipping now and support 64bit Hewlett Packard and Sun Microsystems operating systems, and Linux.
Conformal LEC is priced from $105,000.
Transformal LTX is priced from $95,000.
Conformal LVR will be available in Q3 and is priced from $130,000.
Support for complex, compiled arithmetic operators will be available in Q3 as an additional Conformal option.
The entire line of Verplex formal verification products will be continuously demonstrated at the 39th Design Automation Conference (DAC) in New Orleans from 10th to 13th June 2002.
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