Product category:
Design and Development Software
News Release from: Verplex Systems | Subject: Conformal 4.0
Edited by the Electronicstalk Editorial
Team on 31 July 2003
Full SoC coverage from formal
verification upgrade
The latest release of Conformal provides a comprehensive solution that enables SoC designers and verification engineers to deliver functional bug-free silicon.
The latest release of Conformal provides a comprehensive solution that enables SoC designers and verification engineers to deliver functional bug-free silicon Conformal 4.0 includes enhancements to Conformal LEC logic equivalence checker and integrates new Conformal family products, making Verplex the only equivalence checking company delivering a complete solution for SoC verification
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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BlackTie functional checker from Verplex Systems is the industry's first full-chip multi-million-gate-capacity tool to accelerate the verification of SoC designs.
Formal verification just got faster
Verplex Systems has announced its next generation Conformal Logic Equivalence Checker.
Equivalence checking has become a standard component in an ASIC design flow.
Formal techniques used by equivalence checkers have proven to be the best technology to exhaustively check for errors introduced by design implementation tools or manual engineering change orders (ECOs).
Traditionally, equivalence checkers have forced designers to "black box" much of their SoCs, including memories, complex I/O pads, custom logic and advanced datapath.
Further reading
Verification for high-density FPGAs
Verplex Systems and Xilinx have launched one of the first formal verification environments specifically for the design of high-density FPGAs.
Verification library supports VHDL
Verplex Systems has expanded its Open Verification Library (OVL) to include support for the VHSIC hardware description language (VHDL).
Verification gets physical with complete SoC flow
Verplex Systems has made significant changes to its products to extend its market into the physical domain.
By black boxing these components, equivalence checkers only verified random logic modules, leaving the most complex and error-prone areas of the design unverified.
Conformal 4.0 addresses these limitations found in graphics, multimedia, DSP and communications designs, which often require advanced logic, datapath, memories and custom design modules.
"Verplex continues to deliver breakthrough technology and we are the first to offer a comprehensive equivalence checking solution that enables designers to verify the complete SoC", says Michael Chang, Verplex President and CEO.
"Formally verifying the complete SoC with our best-in-class products enables our customers to exhaustively verify the most complex portions of their designs".
Designs have grown so complex that an independent verification, such as Conformal 4.0, is needed to audit the process by which circuitry is generated to ensure correct results.
Other formal verification tools are not independent, and may require side files, or data clandestinely passed from implementation tools to verify these circuits.
This increases the risk that formal verification uses the same assumptions made during the implementation process, causing it to miss bugs introduced by implementation tools.
Verplex's Conformal 4.0 product family continues to provide best-in-class performance and usability for the entire design flow from register transfer level (RTL) to layout.
It includes five products designed to address the SoC verification challenge: Conformal LEC; Conformal Datapath (DP); Conformal Logic Transistor Extractor (LTX); Conformal Memory (MEM); and Conformal Layout Versus RTL (LVR).
All operate within the same user interface, were designed for ease of use and share similar debugging approaches.
Conformal 4.0 enhances Verplex's flagship product - Conformal LEC - which performs RTL-to-gate and gate-to-gate equivalence checking.
Among the enhancements are improvements in performance, ease of use, Verilog 2001 support, hierarchical comparison, design mapping and the Verplex schematic viewer.
To address the increases in design size and complexity, Verplex continues to improve performance and memory usage within Conformal LEC.
Users will benefit from up to 10x performance improvement for gate-to-gate comparisons and up to 5x performance improvement for RTL-to-gate comparisons.
Memory usage was also improved and users will benefit from up to 30% less memory consumption.
Conformal LEC includes numerous ease-of-use enhancements, including a schematic viewer, value annotation on the source code browser for error diagnosis, on-the-fly ECO editing for design validation, and automatic multiplier analysis.
The Verplex schematic viewer improves performance by using a tightly integrated environment.
This integration enables users to display unlimited schematic sessions with a single license and includes formal verification specific functions such as interactive prove and automatic pruning of non-controlling logic.
Source code value annotation and tracing further improves error diagnosis by displaying error patterns on the source code and enabling the user to identify the source of the error by tracing drivers and loads.
Expanded what-if capability enables the user to modify the design and validate the modification without leaving the Conformal environment, saving hours in debug and iteration time.
With this release, Conformal LEC expands its language support to include support for Verilog 2001.
This enables more efficient capture of design RTL with constructs such as multidimensional arrays, signed arithmetic extensions, generate statement, combinational logic sensitivity, and re-entrant tasks and functions.
Conformal LEC provides the most complete support for Verilog 2001 features used within major synthesis and simulation tools.
Hierarchical comparison and design mapping were also enhanced within Conformal LEC.
Hierarchical comparison is often recommended for large designs to reduce run times and improve debug when design errors are found.
Capabilities were improved to include enhanced module boundary constraint generation and intelligent module flattening.
Conformal LEC further improves its mapping capabilities to address common naming conventions used within implementation tools and to improve designer efficiency in completing this step in the process.
The design-mapping step of the equivalence checking process aligns verification points between two designs being compared and these points must be consistent to achieve successful verification.
Conformal 4.0 integrates recently announced Conformal DP to address requirements of high-performance SoC designs such as applications in graphics, multimedia, DSP, and communications that often use advanced datapath optimisations.
Formally verifying advanced datapath has traditionally been a challenge for equivalence checking.
Verplex has introduced technology capable of verifying a wide variety of datapath structures.
Designers are now able to automatically verify flat datapath modules, complex merged operators, advanced pipelining techniques, and carry-save architectures.
SoC designs frequently include custom I/O cells and designers are leveraging custom design techniques to meet performance requirements.
Conformal 4.0 integrates Conformal LTX into its environment and has added improved transistor schematic and analysis capabilities that improve the user's ability to efficiently compare designs.
Conformal LTX automatically abstracts gate-level models from transistor-level circuits.
This enables formal verification between the RTL model used for design simulation and the actual transistor circuit integrated prior to tapeout.
It ensures that the system verification performed throughout the entire design process is valid by proving the consistency between the simulation model and actual circuit.
The abstracted models may also be used within other applications, including automatic test pattern generation (ATPG), simulation acceleration or emulation.
Memory typically occupies more than half of the die area on SoC designs and trends indicate that embedded memory content is increasing in terms of size and complexity.
Historical memory verification methods involved the use of simulation with all of its drawbacks such as challenging debug, degraded quality of verification, and increased risk of expensive silicon respins due to missed bugs.
The simulation approach is also time consuming, particularly at the transistor or Spice level where memories are designed.
Additionally, the simulation approach is incomplete, proving that designs are free from functional errors under only tested conditions, risking that bugs will slip past to final silicon.
Verplex's Conformal MEM offers an exhaustive verification solution that addresses deficiencies of traditional approaches to memory verification.
Through the use of equivalence checking, 100% exhaustive coverage and fast system-level verification are achieved.
Conformal LVR further expands traditional equivalence checking to enable verification of the final layout.
Previously, equivalence checking verified designs through the final gate-level netlist, which created a verification hole by not ensuring that the final Spice netlist was consistent with the golden RTL.
Conformal LVR enables formal verification of the final Spice netlist against the golden RTL or final gate-level netlist to ensure that the design taped out is functionally equivalent with golden RTL and the final gate-level netlist.
The entire Conformal product family is available now.
US price for a three-year, time-based licence for Conformal LEC is priced from $57,600.
Additional packages are available for the complete Conformal product family, which is supported on Hewlett Packard HP-Unix, Sun Microsystems Solaris, IBM AIX and Linux operating systems platforms.
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