Logic libraries cut silicon costs

Long known in the embedded memory market, Virage Logic is extending its role to the broader category of semiconductor IP platforms with its first foray into logic components.

Long known as a leader in the embedded memory market, Virage Logic is extending that role to the broader category of semiconductor IP platforms with its first foray into logic components.

With its new family of area, speed and power (ASAP) logic products, which includes the ASAP high-speed (HS) metal programmable cell library and the ASAP high-density (HD) standard cell library, Virage Logic is slashing not only the price and power consumption of the overall chip, it is also improving performance.

Targeted at high growth markets such as consumer, communications and networking, graphics, and portable and handheld devices, the new ASAP logic products typically deliver over a 20% increase in logic block area usage.

Silicon proven on a variety of process geometries (0.25, 0.18 and 0.13um) at leading integrated device manufacturers (IDMs), the ASAP Logic product line is being first introduced to fabless semiconductor customers on TSMC's 0.13-micron logic process.

"Yamaha's high volume digital audio applications are based on designs that are quite area-sensitive", said Yukichi Ono, senior engineer, Semiconductor Division, Yamaha Corporation.

"Our first experience with Virage Logic's ASAP Logic architecture resulted in around 20% reduction in area.

With these dramatic results, we have decided to standardise on Virage Logic's ASAP Logic for many Yamaha designs".

The underlying architecture provides the same performance with shorter cell sizes as compared to competitive standard cells.

Through its patented routing and cell architecture, the ASAP Logic products are ideally suited for deep sub-micron applications where optimised routability and minimised power consumption are key.

"Because we believe that highly reliable SoC designs require specialised components in order to meet demanding specifications and time-to-market pressures, we are delivering application-optimised semiconductor IP platforms that are built on advanced technology in both the memory and logic arenas", said Adam Kablanian, CEO and president, Virage Logic.

"We were the first to introduce both a self-testable and repairable embedded memory, as well as a nonvolatile embedded memory that is manufacturable in a standard CMOS logic process.

Now, we are the first to introduce commercially available metal programmable cell libraries that enable significant mask cost reduction for 130 and 90nm process geometries".

With the ASAP HS metal programmable cell library, Virage Logic has overcome a key barrier to low- and medium-volume SoC implementation - high mask costs without causing any performance degradation.

Because of its advances in pin accessibility and power routing, the HS metal programmable cells provide similar area and performance as commercially available conventional standard cells without the penalty of all-layer costs.

If a revision is needed, the designer only has to redesign the block, a few metal and via masks, thereby saving hundreds of thousands of dollars by preserving all other masks.

In order to reduce the overall cost of silicon, Virage Logic's ASAP HD standard cell library leverages the ASAP logic superior place-and-route and cell architecture that is ideal for larger numbers of metal layers.

Additionally, the architecture provides significantly increased pin accessibility and eliminates cell placement blockage from the power grid.

The standard cells deliver, at minimum, a 20% logic block area savings compared to any conventional standard cell architecture.

Depending upon the overall chip architecture, this may result in a 10% reduction in overall chip size and cost, making it ideal for high volume applications such as consumer products.

For most applications, a 10% cost savings can double chip profitability.

For example, in a 130nm logic process, a 10% savings for one million units can represent a dollar savings of $1 million to $10 million, depending on chip size.

Availability and Pricing The ASAP HS metal programmable cell library licensing fee starts at $50,000 (US list price) per design, and the ASAP HD standard cell library licensing fee starts at $25,000 (US list price) per design for fabless customers.

Both products are available now on TSMC's 0.13-micron standard logic process.

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