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News Release from: Virage Logic
Edited by the Electronicstalk Editorial
Team on 25 February 2003
Zorian to present at DATE
Yervant Zorian, Chief Scientist and Vice President of Virage Logic, will present a tutorial on Monday 3rd March 2003 at the DATE conference in Munich.
Yervant Zorian, PhD, the Chief Scientist and Vice President of Virage Logic, will present a tutorial on Monday 3rd March 2003 at the Design, Automation and Test in Europe (DATE) conference in Munich, Germany As a part of the IEEE Computer Society TTTC Test Technology Educational Programme (TTEP) 2003, the tutorial will focus on infrastructure IP for system-on-chip yield
This article was originally published on Electronicstalk on 22 Oct 2002 at 8.00am (UK)
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Dr Zorian, current Vice President of the IEEE Computer Society for Technical Activities, Editor-in-Chief emeritus of the IEEE Design and Test of Computers and past chair of the IEEE's TTTC, will discuss key trends and challenges resulting in manufacturing susceptibility and field reliability that necessitates the use of such IP.
Infrastructure IP ensures the manufacturability of the SoC to achieve the optimum levels of chip yield and reliability.
The tutorial will concentrate on several examples of embedded IP for test, diagnosis, repair and fault tolerance.
"We are pleased to have the opportunity to speak at this year's DATE conference and to discuss trends and strategies that are earmarking the best in manufacturing and reliability", said Adam Kablanian, CEO and President, Virage Logic.
"Infrastructure IP is at the heart of our key strategic initiative to deliver application-optimised semiconductor IP platforms based on memory, logic and I/Os".
Dr Zorian added that infrastructure IP leverages the manufacturing knowledge and feeds back the information into the design phase.
In fact, every single phase in the IC realisation flow affects yield and reliability.
He continued that this includes the design phase, prototyping or production ramp-up, volume fabrication, test, assembly, packaging and even the postproduction life cycle of the chip.
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