Technology-optimised platforms on show at DAC

Edited by the Electronicstalk editorial team May 28, 2003

Virage Logic will demonstrate the key benefits of its newly announced technology-optimised platforms at this year's Design Automation Conference in Anaheim, California.

Virage Logic will demonstrate the key benefits of its newly announced technology-optimised platforms at this year's Design Automation Conference in Anaheim, California.

In addition, the DAC conference programme will include presentations by Virage Logic executives on IP business model and SoC test issues.

Virage Logic's technology-optimised platforms aim to meet the critical requirements of reducing silicon costs and failure risks, while boosting performance and ensuring high manufacturing yields for a particular foundry or integrated device manufacturer (IDM) process.

By providing silicon-proven, integrated IP that is compatible with all the major EDA flows, Virage Logic's technology-optimised platforms address the needs of complex and mainstream SoC designs.

The new technology-optimised platforms will be featured at the Virage Logic booth (#1735) and suites (#2602).

In addition, Virage Logic will showcase some of its foundry, EDA and IP partners in jointly delivered overview presentations in its suites.

In addition, Virage Logic engineering director Mike Colwell will be a copresenter of "SoC design solutions using Virage Logic and Synopsys Galaxy" at Synopsys suite (#2614) at 0900 on Monday 2nd June.

Raj Singh, Vice President of Worldwide Sales for Virage Logic, will participate in an FSA Management Forum Day panel session entitled "IP business models".

This session will help delegates learn to navigate through a host of business models, licensing issues and technical hurdles.

They will also learn how to shorten the time it takes to use third-party IP.

On Thursday 5th June Virage Logic's Vice President and Chief Scientist Yervant Zorian will lead a conference session entitled "Novel approaches in test cost reduction".

Dr Zorian will also conduct an all-day "SoC test strategies" tutorial on Friday 6th June.