No rest for panellists in Paris

Edited by the Electronicstalk editorial team Feb 9, 2004

Virage Logic is taking an active role in panel discussions at this month's Design Automation and Test in Europe (DATE) conference in Paris.

Virage Logic is taking an active role in panel discussions at this month's Design Automation and Test in Europe (DATE) conference in Paris.

In addition, the company will announce new industry partnerships and highlight key customer successes on booth 2050.

Dr Yervant Zorian, Virage Logic's Vice President and Chief Scientist, is the organiser of the DATE conference's Executive Track programme, which includes four sessions: "Managing design complexity in 90nm technology", "The future of EDA: CEO perspective", "Determining the value of test" and "Advanced solutions for SoC design".

Jim Ensell, Virage Logic's Vice President of Marketing and Chairman of the Fabless Semiconductor Association (FSA) IP Committee, will also participate in the panel session on "Common ground for measuring IP quality".