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ASIC initiative allows mixed logic designs

A Virage Logic product story
Edited by the Electronicstalk editorial team Mar 17, 2004

Until now, ASIC designers have generally been limited to one logic library per ASIC design.

Until now, ASIC designers have generally been limited to one logic library per ASIC design.

All that has changed with the release of the Kawasaki Microelectronics Matrix ASIC strategic initiative that enables customers to mix and match logic components from several different libraries to meet specific design objectives.

All the libraries currently offered by Kawasaki for this initiative come from Virage Logic Corp.

As a result of this initiative, designers can now mix and match libraries with different voltage thresholds and different cell heights.

In addition, designers can mix standard cell libraries with metal programmable libraries for cost effective reversions and prototypes.

This multi-million-dollar agreement grants Kawasaki wide access to Virage Logic's Area, Speed and Power (ASAP) Logic product portfolio for TSMC's and UMC's 0.13um and 90nm processes with guaranteed support for future processes to come.

All ASAP Logic libraries are based on Virage Logic's proprietary and patented routing methodology and cell architecture that has been used by semiconductor manufacturers worldwide over the last seven years.

Each ASAP Logic library comes with hand-optimised architecture, circuit design and layout to meet specific design requirements such as desired performance, lowest power consumption, and minimised raw cell area.

All libraries are correlated to silicon for maximum accuracy and predictability of results.

Specific libraries to be offered by Kawasaki include the ASAP Logic High-Density (HD) and Ultra-High-Density (UHD) standard cell libraries and the ASAP Logic HD and High-Speed (HS) Metal Programmable cell libraries.

Virage Logic's ASAP Logic HD Library targets high performance design needs and typically delivers an increase of more than 20% in logic block area utilization.

The ASAP Logic UHD Library delivers 30% area improvement while reducing dynamic power consumption 20% compared with conventional standard cell products.

In addition, Virage Logic's ASAP Logic metal programmable cell libraries bring tremendous advantage in terms of cost management and design flexibility while having minimal impact on design area.

Logic designed with metal programmable cell libraries can be functionally reprogrammed by changing only a few metal and via masks, saving hundreds of thousands of dollars by preserving all of the other masks.

"Given the important role libraries play in our Matrix ASIC initiative, our selection of Virage Logic as our library partner is very significant", said Hisaya Keida, General Manager, Product Marketing and Development Department of Kawasaki.

"In order to make this new initiative a success and a viable alternative for our customers, we needed to make sure that our libraries would be robust, silicon-proven and technologically advanced.

Virage Logic provides all of those attributes and more".

"The Matrix ASIC initiative is very forward-looking and demonstrates Kawasaki's commitment to advanced technology that really solves customers' design challenges", said Jim Ensell, Virage Logic's Vice President of Marketing.

"It is extremely gratifying to know that Virage Logic's libraries are central to this innovative new approach".

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