Product category:
Intellectual Property Cores
News Release from: Virage Logic | Subject: Technology-Optimized Platform and ASAP Logic
Edited by the Electronicstalk Editorial
Team on 26 March 2004
IP runs on latest Chartered/IBM 90nm
process
Virage Logic's Technology-Optimized Platform will be made available on the jointly developed Chartered Semicondutor Manufacturing and IBM 90nm manufacturing process.
Virage Logic's Technology-Optimized Platform - as well as its Area, Speed and Power (ASAP) Logic metal programmable cell libraries - will be made available on the jointly developed Chartered Semiconductor Manufacturing and IBM 90nm manufacturing process SoC designers can now benefit from seamless, easy access to Virage Logic's highly differentiated, silicon-proven intellectual property (IP) as part of the semiconductor industry's first common cross-foundry design enablement programme starting at 90nm, announced by IBM and Chartered
This article was originally published on Electronicstalk on 22 Oct 2002 at 8.00am (UK)
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LSI Logic has licensed ASAP metal programmable cells from Virage Logic for use in its RapidChip silicon platform.
"The unique challenges presented by deep submicron technologies like 90nm and beyond call for silicon-proven and highly optimised IP offerings.
Virage Logic is a long-standing Chartered partner, and we are pleased to have its Technology-Optimized Platform and ASAP Logic metal programmable cell libraries available for our joint 90nm manufacturing process platform with IBM", said Kevin Meyer, Vice President of Worldwide Marketing and Services at Chartered.
"Virage Logic's innovative, quality-focused offering for the joint platform will provide designers the confidence and complete flexibility they need when designing at 90nm".
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Virage Logic has strengthened its relationship with Atmel by expanding its license agreement to include the company's Area, Speed and Power (ASAP) Memory product line on the 0.13-micron process.
"We are working closely with Virage Logic to deliver a 90nm library that will allow both IBM and Chartered customers to realise the potential of our advanced CMOS 9SF process while minimising their costs and risks", said Jim Doyle, Vice President, Foundry Manufacturing Services, IBM Systems and Technology Group.
The patented architecture in the Virage Logic ASAP Logic metal programmable cell libraries provides similar area and performance to commercially available conventional standard cells without the penalty of all-layer mask costs.
If a design revision is needed, customers can regenerate only a few metal and via masks, thereby preserving all other masks and saving hundreds of thousands of dollars.
"Our collaboration with IBM and Chartered is strategic to our 90nm platform plans.
We are very pleased that our 19 licensed semiconductor IP customers on 90nm now have access to the IBM/Chartered foundry technology", said Jim Ensell, vice president of marketing for Virage Logic.
"This collaboration broadens the availability of our silicon-proven, single-source semiconductor IP platform offering and will provide our mutual customers with greater flexibility in manufacturing choices".
Virage Logic's Technology-Optimized Platforms are based on the ASAP Memory High-Density (HD) memories, the ASAP Logic HD standard cell libraries, and the Base I/O libraries.
These platforms help customers expedite the creation of next-generation SoCs by providing silicon-proven IP optimised for a targeted technology node and process.
Technology-Optimized Platform customers have optional access to Virage Logic's rich portfolio of highly differentiated IP including the STAR Memory System, the ASAP Memory High-Speed (HS) and Ultra-Low-Power (ULP) product lines, the ASAP Logic Ultra-High-Density (UHD) standard cell libraries, the patented ASAP Logic HD and HS metal programmable cell libraries, and access to specialty I/Os.
The Virage Logic ASAP Logic products contain application-optimised libraries targeted to unique market requirements and are based on Virage Logic's proprietary and patented routing methodology and cell architecture.
ASAP Logic metal programmable cell libraries are used in SoC designs to economically enable functional reprogrammability by changing only a few metal and via masks.
Virage Logic's Technology-Optimized Platform and ASAP Logic metal programmable cell libraries will be available on the Chartered and IBM joint 90nm manufacturing process platform starting in the second quarter of 2004.
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