Product category:
Intellectual Property Cores
News Release from: Virage Logic | Subject: IPrima Mobile platform
Edited by the Electronicstalk Editorial
Team on 01 July 2004
IP platform focuses on SoC power
consumption
One of the unrelenting challenges facing SoC designers today is power management, particularly in low-power, battery-operated microelectronics.
One of the unrelenting challenges facing SoC designers today is power management, particularly in low-power, battery-operated microelectronics that serve as the basis for any number of ubiquitous consumer electronics products such as cellphones, PDAs and handheld gaming platforms Ironically, the one element in SoCs that has not shrunk along with process geometries is static power
This article was originally published on Electronicstalk on 22 Oct 2002 at 8.00am (UK)
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In fact, it has grown exponentially, in inverse proportion to the overall size of the SoC.
To help designers address this challenge, IPrima Mobile is an application-optimised semiconductor IP platform claimed to significantly minimise and effectively manage power dissipation without paying a performance penalty.
IPrima Mobile is the first offering in Virage Logic's IPrima family of application-optimised semiconductor IP platforms.
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"Portable consumer and wireless personal communication products will be market drivers for the semiconductor industry over the next five years".
"Growth rates for many of these products will average more than 30% annually", said Morry Marshall, Vice President Strategic Technologies at Semico Research Corp.
"The potential power savings and longer battery life offered by the IPrima Mobile platform will provide a real competitive advantage to Virage Logic's customers".
The IPrima family of application-optimised semiconductor IP platforms brings together a wide range of technology-leading IP components in a single, integrated IP platform comprising memories, logic and I/Os.
IPrima Mobile enables a broad range of power management methods to control both static and dynamic power consumption; including such advanced optimisation techniques as full block-level voltage islands, clock gating, mixed-transistor threshold voltage support, voltage frequency scaling, back biasing and state retention standby mode.
With IPrima Mobile, designers can determine the optimum level of power dissipation reduction for their application's performance requirements.
"IPrima Mobile builds on Virage Logic's three-plus years of silicon-proven low-power IP products to provide SoC designers with a single, integrated IP platform that enables them to efficiently develop consumer products with longer battery life and lower electromagnetic interference (EMI) emissions", said Jim Ensell, Vice President of Marketing at Virage Logic.
"By delivering up to 20x reduction in static and 80% reduction in dynamic power dissipation, IPrima Mobile gives our customers the ability to rocket past their competitors in terms of battery life, one of the key features consumers care about".
"We have used Virage Logic memories with many of our designs; however, our latest SignaKlara embedded technology used in a wide range of portable and wearable devices required ultra-low-power and ultraminiature IP", said Peter Balsiger, President of Dspfactory.
"We selected the IPrima Mobile memories and standard cells after an extensive evaluation resulted in significant power and area savings that are required for our latest designs".
To fully maximise IPrima Mobile's advanced power-optimisation features, Virage Logic has established strategic partnerships with leading electronic design automation (EDA) tools developers, IP companies and foundries.
This ensures a complete and reliable design flow, support for protocols such as the ARM Intelligent Energy Management (IEM) technology, and optimisation of performance and energy dissipation with respect to manufacturing costs.
"Optimising power consumption has become a system-level issue".
"To generate the best combination of optimal energy dissipation and adequate computing performance, enhanced EDA tools and optimised IP platforms must work smoothly together", said Eric Filseth, Vice President of Marketing for Digital IC Implementation at Cadence Design Systems.
"Virage Logic's IPrima Mobile was designed to work with our Cadence Encounter low-power design flow, the leading solution to analyse and optimise power for nanometre designs".
"It's significant that Virage Logic is making its first IPrima Mobile platform offering available on TSMC's 0.13-micron process", said Edward Wan, Senior Director of Product Marketing in Design Services at TSMC.
"The consumer electronics market is an important one and IPrima Mobile's power-optimisation techniques, together with TSMC's outstanding manufacturing capabilities, will provide significant benefits".
Virage Logic's IPrima family of application-optimised semiconductor IP platforms delivers integrated, technologically advanced and differentiated IP and supports well-defined system-level design methodologies targeted to specific market applications.
The IPrima Platforms meet the critical requirements of reducing SoC costs, boosting performance and ensuring reliability, while satisfying shrinking development budgets and improving time-to-profitability.
Virage Logic's IPrima family of application-optimised platforms include products for market segments such as consumer, data communications and networking, computer and graphics, and portable and handheld.
The IPrima platforms include optimised components such as: memory IP products crafted for application-specific requirements in terms of type, size, area, performance and power dissipation; standard cell libraries to implement customer-specific differentiation and high-value system blocks; and input/output (I/O) cells for basic and high-performance, application-specific interfaces.
The Virage Logic IPrima Mobile platform is available now on the TSMC 130nm process.
Support for additional foundries and process technologies from 130 to 65nm will also be made available.
IPrima Mobile Platform pricing starts at $150,000.
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