Platforms run on Tower CMOS process

Virage Logic's Technology-Optimized Platforms are to be made available on Tower Semiconductor's 0.13-micron CMOS processes.

Virage Logic's Technology-Optimized Platforms are to be made available on Tower Semiconductor's 0.13-micron CMOS processes.

Under the terms of a new agreement, Tower customers can access Virage Logic's Technology-Optimized Platforms - comprising highly differentiated, silicon-proven embedded memories, standard cell logic libraries and I/O libraries - on Tower's 0.13-micron TS13SL (standard logic) process, followed by support for its 0.13-micron TS13LP (low power) process.

In addition, Tower customers will have access to Virage Logic's rich portfolio of highly differentiated IP including the Self-Test and Repair (STAR) Memory System and the patented Area, Speed and Power (ASAP) Logic metal programmable cell libraries.

Because of the long-standing partnership between the two companies, Virage Logic was given early access to Tower's process and significant elements of the Virage Logic Technology-Optimized Platforms are already silicon-proven on Tower's 0.13-micron process.

"We selected Virage Logic because of our mutual success in previous technology generations, silicon-proven libraries on our process and their commitment and focus on delivering highly differentiated IP", noted Doron Simon, President, Tower USA.

"As we introduce our 0.13-micron offering, it is critical that we work with a partner that has experience in advanced process technologies".

"Our growing worldwide customer base can now gain a competitive advantage in terms of cost and performance".

"We are pleased to extend our successful partnership with Tower to include support of Tower's most advanced technologies in its world-class fab with our Technology-Optimized Platforms", said Adam Kablanian, President and Chief Executive Officer of Virage Logic.

"In addition, with access to the STAR Memory System, which substantially reduces test costs and improves overall yield, and our patented ASAP Logic metal programmable libraries, which save configuration costs by reprogramming only a few masks, Tower's customers can realise significant savings and achieve a shorter time to volume".

Building on its differentiated technology and market leadership position, Virage Logic's Technology-Optimized Platforms, which are custom-tuned to a target manufacturing process, aim to meet the critical requirements of reducing design time, silicon area and design risk, while boosting performance and enhancing manufacturing yields.

By providing silicon-proven, fully characterised IP that is tuned to all major electronic design automation (EDA) design tools and flows, Virage Logic's Technology-Optimized Platforms address the needs of complex and mainstream SoC designs.

Virage Logic's Technology-Optimized Platforms are based on the ASAP Memory High-Density (HD) memories, the ASAP Logic HD Standard Cell libraries, and the company's Base I/O libraries.

Technology-Optimized Platforms help customers expedite the creation of next-generation SoCs by providing silicon-proven IP optimised for a targeted technology node and process.

Technology-Optimized Platform users have optional access to Virage Logic's rich portfolio of highly differentiated IP including the STAR Memory System, the patented ASAP Logic HD and HS metal programmable cell libraries, and access to specialty I/Os such as SSTL, HSTL, PCI, PCI-X, and USB1.1.

Front-end views for Virage Logic's Technology-Optimized Platforms for Tower's 0.13-micron process are expected to be available by Q3 2004.

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