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News Release from: Virage Logic
Edited by the Electronicstalk Editorial
Team on 22 October 2004
Yield optimisation panel features at ITC
Virage Logic Corp is to host an exclusive luncheon panel session moderated by EE Times' Nicolas Mokhoff on 26th October 2004 at the International Test Conference in Charlotte, North Carolina.
Virage Logic Corp is to host an exclusive luncheon panel session moderated by EE Times' Nicolas Mokhoff from 1030 to 1230 on 26th October 2004 at the International Test Conference (ITC) in Charlotte, North Carolina Test industry luminary and Virage Logic Chief Scientist and Vice President Dr Yervant Zorian will join a panel of several select Virage Logic Self-Test and Repair (STAR) Memory System customers who will discuss their design approaches and techniques, and relate their experiences with Virage Logic's innovative and highly integrated embedded memory test and repair system
This article was originally published on Electronicstalk on 22 Oct 2002 at 8.00am (UK)
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Panelists include Fred Fischer, distinguished member of Agere Telecom's technical staff; Frank Hering, Hardware Engineering Manager, Chip Integration, ATI; Dr Samy Makar, Senior Hardware Engineer, Azul Systems; and Kurt Wolf, Director of IP and Library Marketing, TSMC.
Delegates will be seated among the panellists during the lunch to facilitate further discussions.
Virage Logic will also participate in the corporate presentations segment of ITC.
Dr R.
Mouli Chandramouli, Director of STAR Memory System Marketing, will present "Leveraging IP design for optimum manufacturability", during session C5.1 at 0800 on 28th October 2004.
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