SoC design seminars address nanometre challenges

Virage Logic is bringing together some the industry's most formidable players to help SoC designers accelerate silicon success at all levels of the nanometre design process.

In an industry plagued by nanometre design challenges that escape few and impact many, Virage Logic Corp aims to continuously delivers better, higher quality semiconductor IP solutions that reduce overall design costs, boost manufacturing yields and better manage low-power designs.

To this end, Virage Logic is launching an extensive technical seminar series programme throughout the USA, Asia/Pacific and Europe and is bringing together some the industry's most formidable players to help SoC designers accelerate silicon success at all levels of the nanometre design process.

"This programme is designed to provide useful information to help SoC designers succeed in a quickly evolving market heading into the nanometre era", said Jim Ensell, Vice President of Marketing at Virage Logic.

"As technology and market leaders, it's our job to understand and anticipate what SoC designers need, and, more importantly, to deliver solutions and services that allow them to successfully adopt and design in new process technologies".

"Together with our partners Magma Design Automation, MIPS Technologies, PDF/Solutions and several foundry partners, we are providing a complete 360-degree perspective on how to overcome the challenges of power, cost and manufacturing yields that exist in a nanometre world".

Virage Logic and its technology partners - Chartered Semiconductor Manufacturing, IBM, Magma Design Automation, MIPS Technologies, PDF/Solutions and TSMC - have put together an informative technical seminar programme for several US locations.

The programme focuses on how SoC designers can better manage costs, as well as the inherent design challenges associated with nanometre technology.

"Designers face huge challenges in the move to nanometre processes", said Kevin MacLean, Vice President of DFM at PDF/Solutions.

"Designers are squeezed by trying to achieve higher yields with smaller process windows and ever more complex design procedures".

"Key suppliers to semiconductor companies must cooperate to provide the knowledge, tools and methods our customers need to be successful".

"That's why PDF/Solutions is participating in Virage Logic's seminar series".

"Together with Virage Logic, Magma Design Automation, MIPS Technologies and the foundry partners, we can provide tremendous value to attendees on the faster, more effective design and production of nanometre ICs".

The 2005 worldwide seminar series will be kicked off in the USA in Santa Clara, California, on 19th January 2005, followed by Irvine, California, on 20th January, Boston, Massachusetts on 25th January and Austin, Texas, on 27th January.

These day-long seminars begin at 0830 with breakfast and introductions, and include such topics as low-power design and designing for optimal yield, as well as structured ASIC design for lower nonrecurring engineering (NRE) costs.

Registration is now open.

More information on the seminar programme, as well as the upcoming international seminar dates and locations, are available from the Virage Logic website.

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