Product category:
Intellectual Property Cores
News Release from: Virage Logic | Subject: STAR Memory System
Edited by the Electronicstalk Editorial
Team on 11 January 2005
Embedded memory system addresses
nanometre issues
A leading provider of semiconductor IP platforms and pioneer in self-test and self-repair embedded memories, Virage Logic Corp.
Virage Logic Corp continues to break new ground with the announcement of its third-generation Self-Test and Repair (STAR) Memory System The third-generation STAR Memory System remains the only commercially available integrated embedded memory self-test and self-repair solution
This article was originally published on Electronicstalk on 4 Mar 2003 at 8.00am (UK)
Related stories
Memory IP keeps SoC power within budget
Silicon-proven semiconductor IP from Virage Logic has played a key role in the development of Alphamosaic's VC01 multimedia processor, the industry's lowest power video processor.
Memory system boosts automotive camera reliability
The reality of cars that warn drivers of road hazards and track potentially dangerous behaviour of other nearby cars is closer than you think, thanks to MobilEye Vision Technologies.
As such, it provides cost-effective on-chip testing and repairing of designs embedding megabits of memories, but adds significant enhancements that result in faster time-to-market, lower test costs, smaller area and better yield for complex system-on-chip (SoC) designs.
The enhancements provide increased intelligence and automation.
"At Ikanos we strongly believe that the challenges presented by designs using deep submicron technologies demand a comprehensive repairable embedded memory solution to ensure high quality and superior yield", said, Joshua Rom, Vice President of Operations at Ikanos Communications.
Further reading
Memory IP stars in Agere network processor
Agere Systems has adopted Virage Logic's Self-Test and Repair (STAR) Memory System.
Memory system IP proves popular
The Silicon Aware Self-Test and Repair (STAR) Memory System has exceeded 100,000,000 units shipped.
Logic libraries cut silicon costs
Long known in the embedded memory market, Virage Logic is extending its role to the broader category of semiconductor IP platforms with its first foray into logic components.
"We chose Virage Logic's STAR Memory System because of their approach to test and repair as well as extensions to support failure analysis and yield improvement".
In nanometre SoC design, soft errors, memory leakage and the need for high-speed testing are just a few of the challenges plaguing designers.
These challenges are compounded by the ever increasing numbers of memory blocks.
Virage Logic has added intelligence in both the test and repair architecture and algorithms to meet these challenges.
For example, to support high-speed test, critical test functions have been tightly integrated into the memories themselves for extensive and rapid exchange of test patterns and test results between the memories and test engine.
The STAR Memory System's embedded error-correcting-code (ECC) circuitry employs the widely used single error correction, double error detection (SEC-DED) approach to automatically detect and correct soft errors for improved reliability.
As nanometre designs incorporate larger and larger numbers of memories, memory manufacturing defects that impact multiple adjacent memory locations are more prevalent than ever before, and the STAR Memory System has been enhanced to include intelligent test algorithms that detect row and column failures in smaller memories and repair them, ensuring higher yield.
Higher leakage currents common at 90nm and below are addressed by leakage tests to screen out leaking parts and prevent field errors due to reliability issues.
Because SoC designs are becoming increasingly memory-intensive, multiple STAR Memory System instances are often used.
To facilitate chip-level integration of multiple STAR Memory instances, Virage Logic has added chip-level IP called the STAR JPC to the STAR Memory System.
The STAR JPC acts as a chip-level IP infrastructure hub, vastly reducing routing congestion and resulting in area savings and faster timing closure.
The STAR Memory System also delivers powerful capabilities that enhance design productivity.
The STAR Builder is one such productivity booster.
The STAR Builder automates the process of STAR Memory System insertion into the functional hierarchy of the SoC design to accelerate the overall product development schedule.
By automating the insertion task, the STAR Builder helps manage the complex multilevel design hierarchy and cuts down the overall STAR Memory System implementation time from weeks to days.
"The STAR Memory System's ability to automate the implementation of advanced memory test and repair in our complex, embedded memory-intensive SoCs has greatly simplified the insertion of the memory system into the designs", said Mark Arnold, Manager of Agere Systems' Ascot, UK Design Centre.
"The STAR Builder also helped us cut design implementation time, which is an important factor in meeting our time-to-market goals".
"At 90nm and below, memory-intensive SoCs are incredibly complex and therefore bring with them corresponding quality, performance and yield issues", said Jim Ensell, Vice President of Marketing at Virage Logic.
"The significant increased functionality we are delivering in the third-generation STAR Memory System continues to underscore Virage Logic's commitment to helping its customers meet next generation SoC design challenges with advanced integrated self-test and repair technology".
• Virage Logic: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
