Libraries set for shrink to 65nm

TSMC has enlisted Virage Logic Corp to develop libraries to support early users of its 65nm Nexsys process technology.

TSMC has enlisted Virage Logic Corp to develop libraries to support early users of its 65nm Nexsys process technology.

The agreement provides IC designers with much-needed memory compilers for leading-edge system-on-chip (SoC) design.

"At every new technology node, the amount of chip space taken by on-chip memory increases dramatically", said Edward Wan, Senior Director of Design Service Marketing for TSMC.

"At the 65nm node, on-chip memory may occupy more space than logic or any other IP and therefore it's important for our customers to get early access to advanced memory compilers".

Virage Logic is both a long-time provider of library products for a range of TSMC processes and a distributor of TSMC-developed libraries.

Virage Logic is currently working with TSMC in developing 65nm memory compilers and will offer multiple memory architectures for TSMC's 65nm processes to meet specific needs in high-density, high-speed and ultra-low-power applications.

"Our collaboration with TSMC on the 65nm memories underscores Virage Logic's continuing technology leadership at the advanced process technologies of 130nm and below", said Jim Ensell, Vice President of Marketing and Business Development for Virage Logic.

"This agreement with TSMC is the first of our 65nm announcements and provides further validation of Virage Logic's Silicon Aware IP initiative".

"Introduced earlier this year, this initiative calls for the tight integration of physical IP, such as memories, logic and I/Os, with infrastructure IP for test, diagnostics, repair and yield enhancements".

"This combination results in high-yielding, highly reliable semiconductor IP at 130, 90 and now 65nm".

"By significantly increasing yields, sometimes as much as 250%, Virage Logic's Silicon Aware IP removes the barrier to advanced process entry".

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