Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: Virage Logic
Edited by the Electronicstalk Editorial
Team on 10 June 2005
Integrated partner solutions show up at
DAC
Virage Logic will demonstrate how to accelerate silicon success with integrated partner solutions at the 42nd Design Automation Conference (DAC) from 13th to 16th June 2005.
Virage Logic will demonstrate how to accelerate silicon success with integrated partner solutions at the 42nd Design Automation Conference (DAC) from 13th to 16th June 2005 which is being held at the Anaheim Convention Centre in Anaheim, California With the support of 15 VIP partners including leading design services companies, electronic automation design (EDA) and test solutions suppliers, foundry partners and IP providers, Virage Logic will showcase complementary, integrated solutions in a special VIP Partner Pavilion (Booth 406)
This article was originally published on Electronicstalk on 28 May 2003 at 8.00am (UK)
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The extensive partner activities complement Virage Logic's main booth (412), DAC Management Day programmes and hands-on tutorial sessions that will demonstrate the company's leadership at advanced process nodes, which results in high-yielding, highly reliable semiconductor IP, from 130 to 65nm.
Visitors to Virage Logic's VIP Partner Pavilion will learn how Virage Logic and its partners team to provide mutual customers with high quality, silicon-proven, integrated solutions that address design requirements, deliver optimum manufacturability and maximum yield for complex system-on-chip (SoC) designs.
VIP Partner Pavilion participants include: Premier sponsors MIPS Technologies and TSMC; Gold level sponsors Cadence, Chartered, PDF Solutions and Synopsys; Silver level sponsors Alchip, Apache, Magma, Sequence, Silterra and Tensilica; and Bronze level sponsors EL and Associates, Tower and UMC.
Further reading
Metal programmable cells join RapidChip platform
LSI Logic has licensed ASAP metal programmable cells from Virage Logic for use in its RapidChip silicon platform.
TSMC lends library support to SoC design efforts
TSMC and Virage Logic have signed a distribution and support agreement that will provide designers with highly integrated library support and services for SoC design.
Embedded memory aids video-over-networks solution
ViXS Systems has selected the Virage Logic ASAP Memory product for its innovative IP-based video distribution system that delivers broadcast-quality video over networks.
In addition to the demos and presentations in the VIP Partner Pavilion, a VIP lounge martini bar and raffle drawing will be co-hosted with the Premier sponsors on Monday 13th June from 1700 to 1800 during the DAC happy hour.
As part of the DAC tutorial programme, Virage Logic is co-hosting a number of hands-on tutorials with several of its VIP partners.
"Designing extendable cores with low-cost metal programmable technology" will run on Tuesday 14th June from 1400 to 1700 in Room 211AB.
This hands-on tutorial session with CoWare, Magma Design Automation and MIPS Technologies is part of the design for manufacturing track.
Delegates will observe a complete system-level design process, starting from exploring the system architecture and trading-off hardware and system software partitioning.
Registration cost is $75.00 per person with limited seating.
In "Using configurable processors to replace RTL blocks" on Wednesday 15th June from 1400 to 1700 (Room TBA) Tensilica and Virage Logic will cohost a hands-on tutorial session as part of the system-level design and verification track, demonstrating how to design a configurable processor with equivalent performance to hand-coded RTL using Tensilica's Xpres compiler, which automatically analyses C code to determine the best processor configuration and extensions.
The tutorial shows how to evaluate and select the optimal embedded memory IP for Tensilica's Xtensa processor configurations using a web-based portal interface from Virage Logic.
Participants can also expect to learn the performance impact of various memory configurations, and how important it is to tightly match the memory to the processor configuration.
Registration cost is $75.00 per person with limited seating.
Virage Logic is also an invited speaker in VIP partner events organised by Synopsys, Magma and UMC.
Finally, Virage Logic is teaming with TSMC to co-host a thought-provoking lunch panel session: "DFM - the path to profitability".
The round-table session, hosted by Bryan Lewis from Garter, will explore the DFM challenges faced at advanced process nodes and debate such issues as products versus services, front- or back-end investing for DFM, and choosing the right sacrifices or tradeoffs from the perspectives of both the suppliers and users.
The panelists will include: Magdy Abadir, Freescale; Dr Edmund Cheng, Synopsys; Bob Dunnigan, Sigmatel; Anoop Khurana, Ikanos; Kuo Wu, TSMC; and Dr Yervant Zorian, Virage Logic.
The luncheon will be held on Wednesday 15th June at the Anaheim Convention centre, Room 202B from 1130 to 1300.
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