Virage collaborates with UMC at 65nm

Virage Logic is to extend its IP and circuit design expertise to jointly work with UMC to enable optimal IP development for UMC's 65nm process technology.

Virage Logic is to extend its IP and circuit design expertise to jointly work with UMC to enable optimal IP development for UMC's 65nm process technology.

This early engagement partnership will help accelerate adoption of UMC's next generation technology platform and provide a predictable roadmap for enhancements of key IP structures such as memory bit cells.

"UMC's strong commitment to technical leadership is underscored with this agreement", said Alex Shubat, Chief Technical Officer of Virage Logic.

"Because critical IP design intent has been factored in from the start, the resulting process will provide for optimal area, performance, power and yield much sooner than with traditional process development flows".

The agreement calls for Virage Logic to collaborate and consult with UMC's technology and design support teams to analyse process parameters critical for design of key IP elements such as memory, logic and I/Os in order to optimise area, speed, performance and manufacturing yield of systems-on-chips (SoCs).

"At 65nm, design experts and process technology teams need to synchronise much earlier than previous generations to address the new challenges brought by the increasing complexities of deep submicron technology nodes", said Patrick T Lin, Chief SoC Architect, System and Architecture Support Group, UMC.

"Virage Logic's expertise and understanding of the relationship between advanced process parameters and semiconductor IP requirements will be a valuable asset to this effort, and we look forward to their contributions to help accelerate the acceptance of our 65nm process".

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