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Product category: Intellectual Property Cores
News Release from: Virage Logic
Edited by the Electronicstalk Editorial Team on 25 July 2005

Semiconductor IP migrates to 65nm
process

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Virage Logic Corp is delivering optimal-yielding semiconductor IP to two long-standing patrons as they move to 65nm, extending its advanced process technology leadership position.

To make semiconductor manufacturing economically viable at the 65nm process node, the ability to deliver high quality, highly reliable and optimal-yielding semiconductor intellectual property (IP) is essential Virage Logic Corp reckons it is delivering just that to two long-standing patrons as they move to 65nm, extending its advanced process technology leadership position

UMC and Freescale Semiconductor, a long-term 130 and 90nm foundry partner and customer, respectively, have both selected Virage Logic as their first IP supplier for early product development on the 65nm process node.

UMC has engaged Virage Logic to collaborate on analysing process parameters essential for the design of key IP elements for its 65nm process, which is currently in development.

Freescale has licensed Virage Logic's IPrima Mobile Area, Speed and Power (ASAP) Memory and Ultra-Low-Power (ULP) memories and its Silicon Aware IP Self-Test and Repair (STAR) Memory System.

"Virage Logic's long-standing commitment to quality, reliability and manufacturability at advanced process nodes has enabled us to deliver several industry firsts", said Adam Kablanian, Virage Logic's CEO and President.

"We were first to deliver silicon-proven IP at 90nm, first to deliver silicon aware IP that combines physical IP and infrastructure IP for optimal yields, and we're the first IP provider at 65nm".

"We take our leadership position very seriously and are committed to delivering the highest quality IP and support to ensure our customers can proceed with confidence at 130nm, 90nm and now at 65nm".

Virage Logic's focus on manufacturability and yield began with the introduction of the STAR Memory System in 2001 and continues with the company's announcement earlier this year of its Silicon Aware IP, which combines physical IP such as memories, logic and I/Os, with infrastructure IP for test, diagnostics, repair and yield enhancements.

The result is high-yielding, highly reliable semiconductor IP at advanced process nodes.

"The expanded agreements with Freescale and UMC underscore the adoption of our Silicon Aware IP initiative".

"As customers are able to achieve reasonable yields at 65nm, the economic driver for advanced process nodes becomes a reality", added Kablanian.

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