Product category:
Design and Development Software
News Release from: Virage Logic
Edited by the Electronicstalk Editorial
Team on 22 May 2006
Webinar focuses on low-power design
Virage Logic and Cadence Design Systems will present a free online technical webinar titled: "Advanced design methodology for low-power applications: an integrated RTL-to-GDSII approach".
Virage Logic will partner with Cadence Design Systems to present a free online technical webinar titled: "Advanced design methodology for low-power applications: an integrated RTL-to-GDSII approach" The live webinar will be broadcast via TechOnLine on Wednesday 24th May 2006 at 1800 BST
This article was originally published on Electronicstalk on 22 Oct 2002 at 8.00am (UK)
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As power reduction is critical for most designs at the advanced process nodes, and traditional low-power design techniques such as clock gating and mixed-Vt optimisation are no longer adequate for power budget constraints, today's system-on-chip (SoC) designers must now adopt advanced low-power techniques to achieve significant power reduction for their designs.
Virage Logic and Cadence are collaborating on this informative technical webinar to explain how low-power designs implemented with Virage Logic's Ultra-Low-Power Semiconductor IP, in conjunction with the Cadence Encounter digital IC design platform, can meet rigid power budget requirements.
"We are pleased to work with Virage Logic on this complete low-power design flow that provides designers with advanced techniques to meet their power constraints", said Anand Iyer, Product Marketing Director at Cadence.
"The Cadence Encounter digital IC design platform supports complex and low-power designs all the way from RTL-to-GDSII".
"We are committed to providing our customers with integrated solutions; our work with Cadence to provide an advanced design methodology for low-power applications that can help designers achieve significant power reduction results underscores that commitment", said Jim Ensell, Vice President of Marketing and Business Development for Virage Logic.
"We are pleased to offer this complete low-power design flow implementation that helps customers address their critical power budgets and time to market challenges".
This webinar is the third in a series of eight Virage Logic-sponsored educational webinars addressing timely and critical design challenges facing SoC designers.
Each webinar in the series features a different industry-leading company from Virage Logic's VIP Partner Programme and will provide an integrated approach to helping SoC designers successfully leverage the most advanced technologies available for accelerating their silicon success.
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