Product category:
Intellectual Property Cores
News Release from: Virage Logic
Edited by the Electronicstalk Editorial
Team on 10 November 2006
Web seminar promotes core-optimised IP
design
Free online technical webinar covers "Accelerating silicon success for embedded consumer applications with MIPS Technologies and Virage Logic core-optimised IP kits".
Virage Logic Corp is collaborating with MIPS Technologies to present a free online technical webinar on "Accelerating silicon success for embedded consumer applications with MIPS Technologies and Virage Logic core-optimised IP kits" The live webinar will be broadcast via TechOnLine on Thursday 16th November 2006 at 1800 GMT
This article was originally published on Electronicstalk on 22 Oct 2002 at 8.00am (UK)
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Leveraging Virage Logic's Area, Speed and Power (ASAP) Memory and ASAP Logic High-Speed (HS) IP, the series of core-optimised IP kits target the MIPS32 24K, 24KE and 34K families of high-performance, low-power processor cores for manufacture on TSMC's 90nm G process.
The 24K and 24KE processor core families can achieve clock frequencies of 660MHz, using only nominal threshold transistors when implemented with the core-optimised IP kits.
"The performance benefits of the 24K, 24KE and 34K core families have been greatly enhanced with Virage Logic's optimised high speed physical IP", said Pete Del Vecchio, Product Marketing Manager at MIPS Technologies.
"We're pleased to be part of a development effort that enables our customers to minimise their design time and reduce product costs".
"The webinar with MIPS will provide an opportunity for designers to learn how to access the jointly developed core-optimised IP kits specifically tuned to enhance the performance of MIPS processor cores", said Jim Ensell, Senior Vice President of Marketing and Business Development for Virage Logic.
"As the semiconductor industry's trusted IP partner, Virage Logic is committed to providing our customers with integrated solutions to address embedded consumer application challenges".
This webinar is the sixth in a series of eight Virage Logic-sponsored educational webinars addressing timely and critical design challenges facing SoC designers.
Each webinar in the series features a different industry-leading company from Virage Logic's VIP Partner Programme and will provide an integrated approach to helping SoC designers successfully leverage the most advanced technologies available for accelerating their silicon success.
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