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News Release from: Virage Logic | Subject: SiWare
Edited by the Electronicstalk Editorial
Team on 08 April 2008
Memory compilers streamline SoC design
The SiWare Memory compilers and SiWare Logic libraries provide designers with options for maximum flexibility in effectively managing design tradeoffs to meet their specific requirements.
Virage Logic has released the memory compilers and logic libraries for TSMC's 40nm process The new SiWare product portfolio provides semiconductor companies with 40nm physical IP that is designed to enable System-on-Chips (SoCs) to run faster, manage power more efficiently, use less area and achieve higher manufacturing yields
This article was originally published on Electronicstalk on 22 Oct 2002 at 8.00am (UK)
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The SiWare product line, first introduced in October 2007 for the 65nm process, addresses the increasingly complex design requirements placed on physical IP at advanced process nodes.
The SiWare Memory compilers and SiWare Logic libraries provide designers with a complete "dashboard" of options for maximum flexibility in effectively managing design tradeoffs to meet their specific requirements.
As the first commercial IP provider with memory compiler and logic library IP in use on TSMC's 40nm process, Virage Logic offers customers early access to design more competitive chips at reduced risk while helping enable them to take advantage of significant cost savings.
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Primary end markets for SiWare IP on TSMC's 40G process include computer, graphics, networking and storage applications, while primary end markets for SiWare IP on TSMC's 40LP process include wireless, battery-operated and consumer applications.
With its advanced tradeoff capabilities, SiWare Memory users can achieve static power savings of up to 35%, 70% and 90% depending on their selection of the built-in light sleep, deep sleep and shut-down modes available in both the 40G and 40LP memories.
Building on the tradeoff capabilities introduced in the 65nm SiWare product line to enable optimal management of performance, area, power and statistical yield, the 40nm SiWare offering includes advanced built-in power management capabilities that will enable designers to mitigate high power consumption at this advanced process node.
"With the SiWare 40nm announcement, our customers can benefit by taking advantage of Virage Logic's IP products to help differentiate their semiconductor products from competitive offerings with respect to speed, area, power management, standby power and yield", said Brani Buric, Vice President of Product Marketing and Strategic Foundry Relationships at Virage Logic.
"Virage Logic's broad IP portfolio and extensive silicon validation program enables our customers to reduce design risk, shorten time to market and time to volume and lower their development costs".
"Virage Logic IP provides an exceptional value for customers by offering complete product and service packages - from small and large projects, to serving as a full, corporate-wide IP partner".
The SiWare Memory product line of silicon-aware compilers provides power-optimised memories for advanced processes.
These high-performance memory compilers minimise both static and dynamic power consumption and provide optimal yields.
SiWare High-Density memory compilers are optimised to generate memories with the absolute minimum area.
SiWare High-Speed memory compilers are designed to help designers achieve the most aggressive critical path requirements.
Compile-time options for process threshold variants, power saving modes, read and write margin extensions, ultra-low voltage operation and innovative design for at-speed test enable SoC designers to configure optimal solutions for their specific design requirements.
All SiWare memories are fully supported by Virage Logic's STAR Memory System, the company's integrated embedded memory test and repair system.
For repair purposes, the STAR Memory System deploys foundry-developed eFuse for repair signature storage.
The STAR Memory System employs test algorithms tailored for advanced processes for higher product reliability and accelerated time to yield.
The SiWare Logic product line includes yield-optimised standard cells for a wide variety of design applications at 40nm with multiple threshold process variants.
SiWare Logic libraries are offered using three separate architectures to optimise circuits for ultra-high-density, high-speed, or general use.
SiWare Ultra-Low-Power extension libraries provide designers with advanced power management capabilities.
SiWare Memory compilers and SiWare Logic libraries are available now for early adopters of TSMC's 40G and 40LP processes.
Early partners already have internally qualified SiWare IP in silicon.
Virage Logic's qualification process, based on advanced test chip methodologies, is in progress and will be finalised as early as July 2008.
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