Product category:
VMEbus Boards and Assemblies
News Release from: Vmetro | Subject: DPIO2-66
Edited by the Electronicstalk Editorial
Team on 10 April 2003
PMC module provides speedy acquisition
The DPIO2-66 is a third-generation parallel I/O PMC module aimed at high-performance data acquisition applications such as radar, sonar, intelligence systems and image capture and generation.
The DPIO2-66 is a third-generation parallel input/output PMC module aimed at high-performance data acquisition applications such as radar, sonar, intelligence systems, and image capture and generation The DPIO2-66 meets the FPDP (front panel data port) industry standard, but also supports the emerging FPDP II standard for high performance parallel input/output applications up to 400Mbyte/s sustained throughput
This article was originally published on Electronicstalk on 23 Jul 2008 at 8.00am (UK)
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The PMC adapter is capable of a burst transfer rate of up to 533Mbyte/s to the carrier board.
FPDP and FPDP II are the de-facto standards for channelling data between COTS modules in embedded systems, typically in the defence electronics sector.
With a 64bit PCI interface running at 66MHz, the DPIO2-66 is an ideal high-speed sensor I/O interface for PMC carriers such as DSP boards and single board computers.
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The standard DPIO2-66 contains many advanced hardware and firmware features that make it a very powerful engine for recognising complex digital signal formats, such as digital video and framed sensor data, and disseminating them into multiprocessor architectures.
Multiple boards can be set up to work together on the same FPDP bus, distributing input data onto several processing boards with little or no processor intervention.
The advanced linked-list DMA (direct memory access) feature can be programmed to run by itself, driven only by the format and structure of the incoming signal, placing the data directly into the processor memories.
Using the same advanced features, the DPIO2-66 can be used as an output board to generate data to FPDP like a signal source, useful for FPGA inter-board/cabinet communications and sensor emulation purposes.
The programmable hardware logic (FPGAs) used on the DPIO2-66, has been generously dimensioned to allow for custom programming in large volume deliveries for even more specialised parallel I/O purposes such as special framing, pre-processing, transposition, timestamp insertion, specific headers etc.
The FPDP II standard allows for transferring payload data at up to 400Mbyte/s using a 32bit data path clocked at up to 50MHz sampling on both edges.
The DPIO2-66 has a large FIFO (first in first out) memory buffer to even out bursts in the data stream.
The DPIO2 contains two large FPGAs, one at the front-end and one in the host interface end, linked together by a 128K x 32bit FIFO.
The front-end FPGA caters for in-stream data handling, framing and manipulation.
The host interface FPGA handles the PCIbus interface, the linked list DMA controller and advanced data manipulation.
The standard set of data handling features in the DPIO2-66 includes data packing, sample skip and store counters, and module addressing by user bits.
It supports unframed, single or repeating, fixed or dynamic size frame data, and the full range of byte-swap options.
The design is bi-directional under software control.
The DPIO2-66 uses the standard FPDP TTL signal levels, but it can be equipped with a personality module to convert signalling to LVDS.
Personality modules can be custom made to cater for specific data interfaces and signal levels.
As the DPIO2-66 has been targeted for the defence market, it has an inherently rugged design and will also be available in versions with extended environmental specifications. Request a free brochure from Vmetro ...
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