IP core adds serial FPDP datalinks

Available now from Vmetro is a serial FPDP IP core for use on its range of Xilinx Virtex-II Pro FPGA products.

Available now from Vmetro is a serial FPDP IP core for use on its range of Xilinx Virtex-II Pro FPGA products.

The combination of Vmetro hardware, serial FPDP IP, and user programmable FPGAs enables high-performance, highly integrated solutions for a wide range of applications including signal processing, high speed data recorders, real-time imaging, and test systems relying on serial FPDP I/O.

The SFPDP IP core is fully compliant with ANSI 17.1-2003 (serial FPDP) and provides easy creation of point-to-point datalinks with a choice of 1.0625, 2.125 and 2.5Gbit/s FPGA RocketIO connections when using suitable host FPGA cards.

Using fibre optic transceivers, these datalinks can range from just a few meters to more than 10km.

All serial FPDP operating modes are supported, including simple unidirectional links, bi-directional links with dataflow control, copy mode, and copy-loop mode.

These modes offer great flexibility in data transfer and allow for multiple end-points which is especially useful when simultaneously recording and processing raw data.

The IP core occupies only a small logic resource footprint in an FPGA; each serial FPDP interface occupies around 1% of a Virtex II Pro version XC2VP70.

This enables most of the FPGA to be used for user IP even if several serial FPDP interfaces are required on a single device.

"We are seeing customers that have a need for front-end processing of their serial FPDP data, such as collating data from several serial FPDP links into a single data stream", says Dave Barker, Vice President of Business Development for Processing Solutions at Vmetro.

"This offering from Vmetro allows customers to integrate within a single FPGA their front-end processing logic with a fully compliant serial FPDP core".

"For instance, customers can use a Vmetro PMC-FPGA03F Virtex-II Pro PMC to receive and perform the front-end processing of serial FPDP data before sending it to a host CPU node for back-end processing".

The serial FPDP IP core is provided in an EDIF format with obfuscated source for simulation.

The core can be implemented on Vmetro's FPGA products such as the PMC-FPGA03/03F, the VPF1 and the 3CPF1 lines of air cooled and rugged/conduction cooled products.

In addition, customers can implement the core into their own FPGA hardware such as a sensor that will be communicating via serial FPDP to a Vmetro processing or recording system.

Subject to licensing conditions, the core can also be used on non-Vmetro-based FPGA products.

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