Analogue input cards add programmable FPGAs

High-speed analogue input XMC modules with the latest generation Xilinx Virtex-5 FPGA are ideal for real-time applications such as electronic counter measures, radar and telecomms.

Vmetro has announced two high-speed analogue input XMC modules with the latest generation Xilinx Virtex-5 FPGA.

The AD3000 is a single channel 3Gsample/s ADC, and the AD1500 is a dual channel 1.5Gsample/s ADC.

The modules' analogue input utilises either a National Semiconductor ADC083000 or ADC081500 8bit convertor.

Both designs share a common FPGA back-end with either a Virtex-5 SX95T or LX110T FPGA and are directly connected to the analogue input.

This combination of high-speed analogue input and high-performance FPGA processing is ideal for demanding real-time applications such as electronic counter measures (ECM), radar and telecommunications.

"By leverage the performance, power and integration benefits of our 65nm Virtex-5 FPGAs, Vmetro has delivered the industry's first single-board gigasample-per-second ADC XMC modules, providing the required processing performance while meeting customer power budgets", said Per Holmberg, Director of Programmable Digital Solutions Marketing at Xilinx.

"We have been delivering the benefits of 65nm FPGAs since May 2006".

"As one of our early access customers, Vmetro now has a leading edge in their marketplace".

"The AD3000 and AD1500 are not just analogue input cards, they both include a fully user programmable FPGA processing block on an XMC module", says Thomas Nygaard, Chief Technology Officer at Vmetro.

"These boards are changing the rules of the game; in the past, each design was only possible using two separate boards, or one large board because of the power and complexity involved, but not anymore".

An LVPECL trigger input, an LVPECL output, an LVTTL output and the sample clock input are provided on the front panel.

This connectivity allows the AD3000 and AD1500 to be operated in a range of modes, including multi-board synchronous sampling.

The FPGA is connected to two 8Mbyte memory banks of QDRII SRAM capable of accepting the incoming data at full speed from the ADC, and two 128Mbyte banks of DDR2 SDRAM.

Although the use of these memories is defined by the application, they can be used to help maximise the FPGA's DSP processing ability and provide large data buffers.

FPGA reconfiguration is stored in local Flash memory.

The PCI-X interface can be used to send commands to the FPGA to reconfigure itself from a file stored in this Flash.

Alternatively, a JTAG header is provided for code development under the ChipScope Pro development tool chain.

Offboard data links are provided through either PCI-X or PCI via the PMC connectors or high-speed multigigabit-per-second Virtex-5 RocketIO transceivers using the XMC connectors.

There are 16 full-duplex low-power serial transceivers arranged across two XMC connectors.

Each of the 16 transceivers can operate at up to 3.2Gbit/s.

A PCI Express end-point controller is available within the FPGA supporting x1, x2, x4 or x8 PCI Express operation.

This optional built in protocol support frees up FPGA resources and simplifies system design.

Host software support includes Windows, VxWorks and Linux, including drivers for high-speed DMA access between the XMC and host CPU, FPGA reconfiguration and diagnostics.

Example software and firmware are provided for using the National Semiconductor ADC083000 and ADC081500 with the Virtex-5 FPGA as well as the external memory.

A companion product, the XCLK1 clock generator PMC/XMC card can be used to generate up to four low skew and minimal jitter clock signals to the A/D boards.

Both the AD3000 and the AD1500 will be available in XMC and PMC form factors, for air and conduction-cooled environments.

Pricing starts at US $13,995.

The AD3000 is expected to ship in Q3 2007.

The AD1500 is expected to ship in Q3 2007.

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