FPGA processor adopts new mezzanine card standard

The new FMC I/O mezzanine standard will enable a whole new generation of products, such as ADC and DACs, tightly integrated into the FPGA resources of the carrier board.

Vmetro has come up with one of the industry's first FPGA processing engines with support for the new FPGA Mezzanine Card (FMC/VITA 57) standard.

The FPE650's innovative design integrates four Xilinx Virtex-5 FPGAs with two FMC I/O sites and VPX high-speed serial backplane connectivity, allowing I/O and processing capabilities in a single 6U slot.

The FPE650, available in air-cooled and conduction-cooled rugged versions, is designed to tackle the most demanding digital signal processing applications such as electronic countermeasures (ECM), signal intelligence (sigint) and electro-optics (EO).

At the heart of the FPE650 are four fully interconnected user programmable Xilinx Virtex-5 FPGAs.

The FPGAs sites can be fitted with Virtex-5 SX95T, LX155T or FX100T platforms enabling the FPE650 to be optimised for DSP or logic centric designs.

Each FPGA has four directly connected banks of memory to maximise performance.

Two of the FPGAs interface to four 9Mbyte banks of QDR2 SRAM; the other two FPGAs interface to two 9Mbyte banks of QDR2 SRAM and two 640Mbyte banks of DDR2 SDRAM.

"The balance of processing performance, modular I/O and VPX connectivity is very important for demanding applications", comments Thomas Nygaard, Chief Technology Officer of Vmetro.

"The FPE650 excels at this by allowing sensor I/O or system data to be delivered directly to the FPGAs".

"The FPE650 is pioneering use of the new FMC I/O mezzanine standard, opening the door for a whole new generation of products, such as ADC and DACs, tightly integrated into the FPGA resources of the carrier board without the overhead of protocol translation required by other mezzanine standards".

The FPE650 addresses the I/O and data bandwidth requirements of high performance digital signal processing applications with three interconnects features - through FPGA Mezzanine Card (FMC/VITA 57) sites for front panel I/O, through a nonblocking crossbar to help optimise the FPGA topology, and VPX/VITA 46 connections for backplane I/O.

For front panel I/O, each FMC site has 68 differential signal pairs supporting 2Gbit/s datarates per pair and four full-duplex multi-gigabit-per-second connections to enable very large amounts of data to be moved between FMC modules and the onboard FPGAs.

For onboard data movement, high-speed serial links from the FMC sites, the FPGA, and the backplane are routed to a nonblocking crossbar switch.

By configuring the crossbar switch, the connections between these resources to be configured specifically to meet application needs.

For backplane I/O, each FPGA has two x4 full-duplex multi-gigabit-per-second serial ports routed to the VPX backplane with each x4 port able to move over 1Gbyte/s of data.

The FPE650 also provides backplane parallel I/O directly connected to two of the FPGAs.

"Vmetro is one of the first COTS vendors to announce products based on the new FMC standard", states Raj Seelam, DSP Solutions Product Manager at Xilinx.

"The combination of high-speed I/O FMC modules with our latest Virtex-5 SXT FPGA technology makes the FPE650 a very attractive product for a variety of DSP applications".

"The flexibility afforded by the industry-standard FMC specification will greatly enhance the ability of Xilinx and our partners in bringing more focused and comprehensive solutions to the high-performance marketplace".

A Software and HDL development suite for the FPE650 is available from Vmetro, including IP blocks such as DMA and memory controllers and sophisticated examples and utilities for FPGA configuration and development.

The majority of the resources on all the FPGAs are available for user applications.

The will also shortly be announcing a range of FMC modules to be used with the FPE650 and other Vmetro FPGA-based products.

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