MIPS core takes DSP software onboard

Vocal Technologies has demonstrated multiple flavours of xDSL baseband or 802.11 MAC functions on the new Pro Series microprocessor core from MIPS Technologies.

Vocal Technologies has demonstrated multiple flavours of xDSL baseband or 802.11 MAC functions on the new Pro Series microprocessor core from MIPS Technologies.

This capability enables value-enhanced multiprotocol consumer communication SoCs, with smaller die size than can be achieved with a traditional DSP implementation.

The Pro Series family of cores from MIPS Technologies features the CorExtend capability that enables designers to supercharge their design's performance by adding application-specific knowledge and instructions to a 32bit MIPS core.

This capability is unique among industry-standard architectures and underscores the power and ability of a general-purpose microprocessor to subsume the hardwired logic of an SoC.

In turn, engineers can reduce total design costs by reducing silicon area and design time.

"The use of MIPS Technologies' new CorExtend capability provides a very powerful mechanism to extend the performance of an industry-standard architecture in ways that eliminate part of the design effort of DSP-intensive designs", said Dr Victor Demjanenko, CTO of Vocal Technologies.

"Now, MIPS licensees can replace DSP functionality all together by leveraging the work our engineers have done and exploiting the parallelism in the MIPS architecture.

Ultimately, we expect broad adoption of this technology".

"Vocal has given SoC designers a proven pathway to stay ahead of the rapidly changing communications standards with products that leverage and extend the functionality of an industry-standard processor", said Brad Holtzinger, Director of Systems Solutions for MIPS Technologies.

"The MIPS core, with its efficient RISC instruction set and optimised C compilers, used native instructions and the CorExtend capability to perform the signal processing functions.

The result is lower SoC die size and streamlined SoC programming models".

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