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    <title>RSS News Feed for Verisity Design - from Electronicstalk</title>
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    <description>Verisity Design news releases on Electronicstalk</description>
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    <copyright>Copyright (C)2008 Pro-Talk Ltd. All rights reserved.</copyright>
    <pubDate>Fri, 24 Oct 2008 08:00:00 UT</pubDate>
    <lastBuildDate>Fri, 24 Oct 2008 08:00:00 UT</lastBuildDate>
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    <item>
      <title>Novel methodology decimates SoC verification times</title>
      <description>Verisity has developed a new methodology that enables a 10x increase in productivity and improved predictability for automating the verification process at the SoC and system level.</description>
      <pubDate>Thu, 18 Sep 2003 08:00:00 UT</pubDate>
      <category>Verisity Design</category>
      <link>http://www.electronicstalk.com/news/vrs/vrs126.html</link>
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    <item>
      <title>Software aids verification environment development</title>
      <description>eAnalyzer is an intuitive static analysis and verification methodology compliance system that simplifies verification environment development.</description>
      <pubDate>Thu, 18 Sep 2003 08:00:00 UT</pubDate>
      <category>Verisity Design</category>
      <link>http://www.electronicstalk.com/news/vrs/vrs127.html</link>
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    <item>
      <title>Faster verification for PCI Express-based chips</title>
      <description>A new PCI Express e Verification Component (eVC) dramatically shortens the time needed to create a PCI Express-based verification environment.</description>
      <pubDate>Thu, 18 Sep 2003 08:00:00 UT</pubDate>
      <category>Verisity Design</category>
      <link>http://www.electronicstalk.com/news/vrs/vrs128.html</link>
    </item>
    <item>
      <title>Institutions queue up for university programme</title>
      <description>Verisity has significantly expanded its university programme with 22 new university members, bringing the total number of participating academic institutions to 45.</description>
      <pubDate>Tue, 16 Sep 2003 08:00:00 UT</pubDate>
      <category>Verisity Design</category>
      <link>http://www.electronicstalk.com/news/vrs/vrs125.html</link>
    </item>
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      <title>National automates its verification processes</title>
      <description>National Semiconductor has standardised on Verisity's Specman Elite verification process automation.</description>
      <pubDate>Fri, 08 Aug 2003 08:00:00 UT</pubDate>
      <category>Verisity Design</category>
      <link>http://www.electronicstalk.com/news/vrs/vrs124.html</link>
    </item>
    <item>
      <title>Integration aims to speed verification</title>
      <description>Tharas Systems has joined Verisity's Interoperability Partners (VIP) programme to develop an integration between its Hammer hardware accelerator and Verisity's eCelerator testbench acceleration tool.</description>
      <pubDate>Wed, 30 Jul 2003 08:00:00 UT</pubDate>
      <category>Verisity Design</category>
      <link>http://www.electronicstalk.com/news/vrs/vrs122.html</link>
    </item>
    <item>
      <title>Aptix alliance to provide hardware acceleration</title>
      <description>Aptix is to integrate its System Explorer hardware accelerator with Verisity's eCelerator testbench acceleration tool.</description>
      <pubDate>Wed, 30 Jul 2003 08:00:00 UT</pubDate>
      <category>Verisity Design</category>
      <link>http://www.electronicstalk.com/news/vrs/vrs123.html</link>
    </item>
    <item>
      <title>Steady progress for Verisity</title>
      <description>Verisity has published its financial results for the second fiscal quarter ended 30th June 2003.</description>
      <pubDate>Fri, 25 Jul 2003 08:00:00 UT</pubDate>
      <category>Verisity Design</category>
      <link>http://www.electronicstalk.com/news/vrs/vrs121.html</link>
    </item>
    <item>
      <title>Design verification with e</title>
      <description>"Design verification with e", by Samir Palnitkar details a broad range of e-based topics including modelling, constraint-driven test generation, functional coverage and assertion checking.</description>
      <pubDate>Thu, 05 Jun 2003 08:00:00 UT</pubDate>
      <category>Verisity Design</category>
      <link>http://www.electronicstalk.com/news/vrs/vrs118.html</link>
    </item>
    <item>
      <title>Testbench supports more open standards</title>
      <description>To better support system-level design flows, Verisity is supporting a wide variety of open standards through the Specman Elite testbench automation solution, including OVL, PSL/Sugar and SystemC.</description>
      <pubDate>Thu, 05 Jun 2003 08:00:00 UT</pubDate>
      <category>Verisity Design</category>
      <link>http://www.electronicstalk.com/news/vrs/vrs119.html</link>
    </item>
    <item>
      <title>Verification language set for standardisation</title>
      <description>The IEEE Design Automation Standards Committee has approved a project to use the e verification language as a basis for standardisation.</description>
      <pubDate>Thu, 05 Jun 2003 08:00:00 UT</pubDate>
      <category>Verisity Design</category>
      <link>http://www.electronicstalk.com/news/vrs/vrs120.html</link>
    </item>
    <item>
      <title>Added components expand e-verification</title>
      <description>YogiTech has developed three new e-verification components (eVCs) for the AT Attachment Packet Interface (ATAPI), Controller Area Network (CAN) and the Open Core Protocol (OCP).</description>
      <pubDate>Tue, 06 May 2003 08:00:00 UT</pubDate>
      <category>Verisity Design</category>
      <link>http://www.electronicstalk.com/news/vrs/vrs117.html</link>
    </item>
    <item>
      <title>Increased re-use speeds testbench automation</title>
      <description>Available now from Verisity is version 4.1 of the Specman Elite testbench automation solution.</description>
      <pubDate>Thu, 27 Mar 2003 08:00:00 UT</pubDate>
      <category>Verisity Design</category>
      <link>http://www.electronicstalk.com/news/vrs/vrs114.html</link>
    </item>
    <item>
      <title>Training for verification methodology practices</title>
      <description>To meet the increased demand for advanced verification methods, Verisity has set up a new training course - Specman Elite advanced training - that teaches verification methodology best practices.</description>
      <pubDate>Thu, 27 Mar 2003 08:00:00 UT</pubDate>
      <category>Verisity Design</category>
      <link>http://www.electronicstalk.com/news/vrs/vrs115.html</link>
    </item>
    <item>
      <title>Verification components cover popular demand</title>
      <description>Verisity is greatly expanding its offerings of eVerification Components (eVCs) in order to meet the increasing demand for reusable verification components for standard interfaces.</description>
      <pubDate>Thu, 27 Mar 2003 08:00:00 UT</pubDate>
      <category>Verisity Design</category>
      <link>http://www.electronicstalk.com/news/vrs/vrs116.html</link>
    </item>
    <item>
      <title>Mentor joins alliance programme</title>
      <description>Mentor Graphics has become the 100th member of Verisity's Verification Alliance programme.</description>
      <pubDate>Wed, 26 Feb 2003 08:00:00 UT</pubDate>
      <category>Verisity Design</category>
      <link>http://www.electronicstalk.com/news/vrs/vrs113.html</link>
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