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Latchup is no problem for novel JFET design

A Vishay Siliconix product story
Edited by the Electronicstalk editorial team Jun 17, 2003

A new series of JFETs is claimed to eliminate the problem of latchup in amplifier designs.

Siliconix has developed a new series of JFETs claimed to eliminate the problem of latchup in amplifier designs.

A perennial challenge for analogue designers, latchup occurs when several JFETs on the same substrate form a parasitic junction that can turn on unexpectedly, causing excessive current to flow.

The complete new family of "no-latch" monolithic dual JFETs, which includes more than 20 devices, overcomes this problem by providing an exposed substrate connection via an external pin, allowing designers to bias the substrate with a positive potential to prevent a latchup condition.

Monolithic dual JFETs are widely used as a high-performance differential front end for amplifiers in test equipment, industrial process equipment, military monitors, and any other application where high-accuracy data acquisition is needed.

Integrating two transistors on the same substrate ensures that the temperature of both channels is the same.

As a result, performance is more evenly matched across the device's operating temperature range than in implementations with two single-die JFETs.

Until now, designers have needed to use multichip JFETs or additional external components to ensure that no latchup occurs.

With this new family of devices, Vishay provides a significantly less expensive, monolithic alternative available in both the TO-78 and the surface-mount SOIC-8 packages.

The more than 20 devices in the series offer a range of breakdown voltages from 25 to 50V.

For superior low-noise capability, offset/drift voltage ranges from 40mV down to an extraordinarily low 5mV.

This tight gate-source voltage matching minimises errors in front-end amplifiers.

A range of gate-source cutoff voltage ratings from 0.5 to 6V gives designers a wide choice of devices to suit their specific applications.

Samples and production quantities of the new no-latch JFETs are available now, with lead times of six to eight weeks for larger orders.

Pricing starts at less than $1 in 1000-piece quantities.

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A Pro-talk Publication

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