Product category:
Analogue and Mixed Signal ICs
News Release from: Wolfson Microelectronics | Subject: Sanyo ADC
Edited by the Electronicstalk Editorial
Team on 27 June 2002
High-speed convertor uses 0.18-micron
SoC process
Wolfson Microelectronics has narrowed the technology gap between analogue and digital circuits by designing its first high-speed 14bit ADC on a state-of-the-art 0.18-micron process.
Wolfson Microelectronics has narrowed the technology gap between analogue and digital circuits by designing its first high-speed 14bit ADC on a state-of-the-art 0.18-micron process Wolfson is one of the first companies to use 0.18um technology for a high-performance mixed-signal SoC
This article was originally published on Electronicstalk on 13 Apr 2001 at 8.00am (UK)
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The ADC was specifically tailored for integration with a 100k+ gate digital signal processor from Sanyo for next generation automotive entertainment electronic systems.
"There are many factors driving the need for precision analogue, high-resolution and high-speed data converters including the need to reduce cost, size, and power consumption", explained David Milne, CEO and Managing Director.
"At the same time, there are many technical issues to overcome before a product of this complexity can be put into production".
The issues to be overcome include, a reduction in the available signal dynamic range caused by reduced supply voltages in deep submicron processes, increased noise as a result of combining analogue and digital components in a single design and a process technology that is new and untried for high performance mixed-signal circuits.
To achieve high levels of ADC spectral purity, noise ingress must be controlled.
With reduced supply voltages, the signal range is constrained and noise will become a larger component in the design if allowed to remain unchecked.
Use of optimally configured voltage levels in different sections of the circuit, a differential circuit topology, carefully balanced layout, and on-chip and off-chip decoupling strategies were necessary to control the coupling of noise from the high speed digital circuits onto the low level analogue circuits.
Wolfson has elected to use triple well isolation to keep the most sensitive analogue parts physically separate from the digital circuits, limiting the potential for noise from the high speed digital circuits reaching the low-level analogue circuits through references, supplies and substrates.
This necessitated the development of new circuit-level simulation models of the physical coupling paths and parasitic elements, including the substrate and interconnect, parasitic junction capacitances, and package inductances.
In addition, Wolfson worked with the wafer foundry to optimise the process to achieve the performance targets.
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