Product category:
Analogue and Mixed Signal ICs
News Release from: Xicor | Subject: X98023 and X98021
Edited by the Electronicstalk Editorial
Team on 02 April 2003
Front ends boost hi-res monitor
performance
Two new high-speed analogue front ends offer new levels of high resolution video performance for UXGA monitor applications.
Two new high-speed analogue front ends (AFEs) offer new levels of high resolution video performance for UXGA monitor applications Both the 230MHz X98023 and the 205MHz X98021 have three independent channels to capture the red, green and blue (RGB), YUV or SOG video signals sent from personal computers, workstations or video set-top boxes to drive an LCD monitor or LCD projector
This article was originally published on Electronicstalk on 24 Jan 2002 at 8.00am (UK)
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Each channel has an 8bit, fully differential signal path to provide the low noise and high performance needed to support high pixel count monitors.
The X98023 supports UXGA resolutions (1600 x 1200pixel) at a refresh rate up to 85Hz and the X98021 supports UXGA resolutions up to a refresh rate of 75Hz.
Both devices feature a state-of-the-art internal digital phase-locked loop (DPLL) with 64 phase steps and offering significantly improved jitter performance over currently available products.
On-the-fly display mode optimisation is further eased by a unique offset and gain adjustment structure that decouples the gain and offset adjustments, and completely eliminates offset error and drift.
Xicor's DPLLs eliminate the tradeoffs and complexity of traditional analogue PLL solutions to provide sharper images and improved video quality for high resolution monitors, projectors and televisions.
Featuring a programmable analogue input bandwidth from 100 to 780MHz, and a 0.35 to 1.4V analogue input range, the devices operate from a single 3.3V power supply, and have internal 1.8V regulation.
AC or DC input coupling facilities are provided, as is a two-channel input multiplexer.
Typical power consumption is given as 800mW at 230Msample/s for the X98023, and a low PLL long-term clock jitter figure of 250ps peak-peak is also specified at 230Msample/s for the device.
Completely independent 8bit gain and 10bit offset control is provided.
The X98023 and X98021 are fabricated in a generic 0.18-micron CMOS process for easy integration with additional digital functions in future products.
Demonstration boards are available now.
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