Product category:
Design and Development Software
News Release from: Xilinx | Subject: ISE WebPack 9.1i
Edited by the Electronicstalk Editorial
Team on 23 January 2007
Programmable logic design suite is free
online
Xilinx has announced the immediate availability of the ISE WebPack 9.1i release of its free downloadable programmable logic design suite.
Xilinx has announced the immediate availability of the ISE WebPack 9.1i release of its free downloadable programmable logic design suite The new version includes all the features of the 9.1i release of the popular Xilinx ISE Foundation software with full support for optional embedded, digital signal processing (DSP) and real-time debug design flows
This article was originally published on Electronicstalk on 18 Apr 2003 at 8.00am (UK)
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Most notably, ISE WebPack 9.1i software includes the new Xilinx SmartCompile technology, which significantly improves run times by up to 6x faster than the previous version, while maintaining exact design preservation of unchanged logic.
ISE WebPack 9.1i software also includes support for all devices in the Spartan-3A family of FPGAs and select Virtex-4 and Virtex-5 FPGA devices.
New power optimisation features help designers reduce dynamic power by an average of 10%.
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ISE WebPack 9.1i software offers a complete front-to-back FPGA design solution allowing users to immediately begin projects.
By providing integrated tools for HDL entry, synthesis, implementation, and verification in a free downloadable environment, ISE 9.1i helps users rapidly achieve design goals while reducing overall project cost.
This release includes ISE Simulator Lite on both Windows and Linux.
The free MXE-III Starter version is available for download from the Xilinx website giving designers a choice in free HDL verification solutions.
Xilinx delivers the industry's lowest-cost and lowest-power FPGA and CPLD solutions with the most extensive front-to-back Windows and Linux support of any major PLD vendor.
ISE WebPack 9.1i software includes new SmartCompile technology to help designers address the problems associated with re-implementing an entire design with each incremental change.
Such re-implementations take time and introduce risk of disrupting portions of the design not directly involved with the change.
New features in ISE WebPack 9.1i software build on the capabilities of Fmax technology, especially designed to deliver unparalleled performance and timing closure results for high density, high performance designs.
ISE WebPack 9.1i software includes integrated timing closure flow which incorporates enhanced physical synthesis optimisations to provide higher quality of results.
ISE WebPack 9.1i software includes the expanded timing closure environment of the standard ISE 9.1i version - a virtual "timing closure cockpit" - that enables intuitive cross-probing between constraint entry, timing analysis, floorplanning and report views so designers can more easily analyse timing problems.
The integrated timing closure flow incorporates enhanced physical synthesis with improved timing correlation between synthesis and placement timing, resulting in higher quality of results.
New power optimisation in Xilinx Synthesis Technology (XST) and placement, together with improvements in routing, deliver an average of 10% lower dynamic power for the Spartan-3 generation of FPGAs.
Power optimisation improvements in XST also provide power-aware logic optimisations for macro processing on blocks such as multipliers, adders and BRAMs.
Implementation algorithms deploy power-efficient placement strategies and lower capacitance nets within the device to minimise power without sacrificing performance.
ISE WebPack 9.1i software is now available for free immediate download from the Xilinx website.
Offering the most-complete zero cost design environment to the company's rapidly growing base of over 300,000 FPGA and CPLD designers, ISE 9.1i provides support for all members of the Spartan-3A and CoolRunner-II families, as well as select Virtex-4 and Virtex-5 FPGA devices.
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