Product category:
Intellectual Property Cores
News Release from: Xilinx | Subject: Virtex-5 protocol packs
Edited by the Electronicstalk Editorial
Team on 21 February 2007
Protocol packs ease FPGA applications
development
Xilinx has released protocol packs for PCI Express, Gigabit Ethernet and XAUI for its 65nm Virtex-5 family of FPGAs.
Xilinx has released protocol packs for PCI Express, Gigabit Ethernet and XAUI for its 65nm Virtex-5 family of FPGAs The company has also released protocol-specific characterisation reports for Sonet OC-48/SDH STM-16 and CPRI (Common Public Radio Interface)
This article was originally published on Electronicstalk on 18 Apr 2003 at 8.00am (UK)
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Each standard protocol pack includes protocol specific physical layer characterisation reports, interoperability and compliance reports, intellectual property (IP) cores and documentation to facilitate low-risk and efficient implementation of standardised high-speed serial protocols in Virtex-5 FPGAs.
"Xilinx has taken the first step to set a direction for the FPGA industry by offering more than just compliance and interoperability information - now offering protocol packs which include protocol specific characterisation reports and IP", said Jag Bolaria, Senior Analyst at The Linley Group, a leading market research firm.
"Now FPGA customers can take advantage of characterisation data that is typical for ASSPs, which unlike FPGAs are a point product and do not have to deal with a broad range of applications".
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With 12 of the 15 announced Virtex-5 family devices shipping today, the protocol packs serve to further enable rapid customer adoption.
"As the adoption of high-speed serial I/O protocols continues to increase, our Virtex-5 LXT and SXT devices with their low-power RocketIO GTP transceivers are being deployed in a growing variety of applications", said Steve Douglass, vice president and general manager of the Advanced Products Division at Xilinx.
"By providing protocol-specific device characterisation across process voltage and temperature, Xilinx is not only enabling faster design closure and reducing risk, but is also taking a tremendous leap forward in the FPGA business".
Virtex-5 LXT samples have been available since May 2006 and all Virtex-5 available devices are now characterised across process corners, voltage and temperature (PVT) for key transceiver performance specifications (such as transmit jitter generation and jitter tolerance), compliance test suites, and rigorous test programs and with third party devices to ensure predictable performance in user applications.
The RocketIO GTP transceivers in Virtex-5 devices support a multitude of protocols.
With protocol specific characterisation of this kind, users can reduce design cycle time by orders of magnitudes.
To achieve this milestone, Xilinx has employed a layered characterisation methodology testing the common aspects of multiple protocols first and then testing protocol-specific requirements.
In addition to protocol characterisation, each protocol pack provides interoperability certification data of the solution (device, hard and soft IP including PHY and link layers) ensuring compliance with a standard's specifications.
Xilinx actively participates at standards body certification events to ensure compliance.
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