Product category:
Design and Development Software
News Release from: Xilinx | Subject: PlanAhead 9.1
Edited by the Electronicstalk Editorial
Team on 20 March 2007
Design suite simplifies FPGA pin
assignments
The PlanAhead 9.1 design suite delivers an additional option for designers to optimise the maximum performance of 65nm Virtex-5 FPGAs.
Xilinx has announced immediate availability of the 9.1 version of PlanAhead hierarchical design and analysis software with support for its newest high-performance 65nm Virtex-5 and Spartan-3 generation FPGAs Used in conjunction with the Xilinx Integrated Software Environment (ISE) design tools, the PlanAhead 9.1 design suite delivers an additional option for designers to optimise the maximum performance of the company's latest 65nm Virtex-5 FPGAs
This article was originally published on Electronicstalk on 18 Apr 2003 at 8.00am (UK)
Related stories
FPGAs put 90nm process to competitive advantage
A new family of programmable chips aims to propel programmable logic devices further into high-volume, low-cost applications traditionally served by custom chips with fixed architectures.
FPGAs enable novel sporting AV experience
Xilinx has been working with World Audio Visual Entertainment Systems on the world's first wireless AV entertainment system designed to enhance spectator experience at a variety of sporting events.
Leveraging the unique advantages of the Virtex-5 ExpressFabric technology, 550MHz DSP48E slices, and flexible clock management tiles, the PlanAhead 9.1 design suite delivers unprecedented levels of performance - as high as a two speed-grade advantage over competing solutions.
PlanAhead 9.1 includes a new PinAhead technology, offering an environment for fully automatic or semi-automated assignment of I/O ports to physical package pins.
Using PinAhead technology, FPGA designers can assign interface I/O groups to I/O pins simply by dragging into a graphical representation of the FPGA.
Further reading
FPGAs take control at Williams
The BMW WilliamsF1 Team is using Xilinx Virtex-II platform FPGAs as the leading technology in the vehicle control module of the team's 2003 challenger - the WilliamsF1 BMW FW25.
Geometry shrink pays dividends for FPGA users
Xilinx reckons its investment in the industry's most advanced 90nm and 300mm chip-making technology is already paying off for customers.
FPGA-based processors bring 3D biometrics in reach
Xilinx and Pixel Velocity have completed a project that is claimed to provide the world's most advanced 3D facial recognition technology.
PinAhead technology offers FPGA designers an intuitive solution to the complexities of managing the interface between their target FPGA and the PCB.
PinAhead technology provides an interface to analyse the design and device I/O requirements and to define an I/O pinout configuration that satisfies the needs of both the PCB and FPGA designers.
Designers can begin pin assignment prior to having a completed PCB or FPGA netlist, drastically reducing time to market.
PlanAhead 9.1 allows designers to either create their own port list with a GUI interface or import a comma separated values (CSV) spreadsheet.
This allows early decisions to be made permitting the PCB and FPGA designers to begin work much earlier with a much more realistic pinout configuration.
"A growing number of FPGA designers have greatly improved the quality of results for their FPGA designs using PlanAhead", said Salil Raje, Xilinx Director for Design Planning and Verification.
"The addition of our new PinAhead technology offers a unique bridge between optimal quality of results for the FPGA design and early optimised I/O layout for the PCB, extending the team-based design benefits of PlanAhead software".
PinAhead technology allows early and intelligent pinout definition to eliminate a lot of the pinout related changes that typically happen downstream.
Better user control of FPGA pinout early in the design process can also offer significant improvements in performance, avoiding a nonoptimal pinout which causes further delays when trying to meet timing requirements.
By considering the data flow from PCB to FPGA die, optimal pinout configurations can be achieved quickly, thus reducing internal and external trace lengths and routing congestion.
To help users better manage dynamic placement constraints, which may be user assigned or imported from the netlist generated by the ISE Design Tools, PlanAhead 9.1 provides a simplified method for controlling constraints.
Designers are now able to clear placement constraints assigned by the ISE Design Tools without affecting remaining user constraints.
Designers also have the ability to selectively mark a subset of the placement constraints assigned by the ISE implementation tools to be treated as user defined constraints.
The capability with PlanAhead 9.1 to better control logic preservation provides ultimate flexibility while keeping the process intuitive.
In addition to supporting the latest Virtex-5 LX, LXT and SXT devices, PlanAhead 9.1 software extends device support to the company's latest low-cost, high-volume Spartan-3 generation FPGAs including the recently introduced I/O optimised Spartan-3A and nonvolatile Spartan-3AN platforms.
The additional support of four new FPGA device families enables designers across a wide range of applications to take advantage of the industry unique solution offered by PlanAhead 9.1.
The PlanAhead 9.1 design suite is available on all major operating systems as an option to the Xilinx ISE design suite.
Single-user licenses are currently available at a promotional list price of US $2495.
• Xilinx: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
