Product category:
Programmable Logic Devices
News Release from: Xilinx | Subject: Spartan-3
Edited by the Electronicstalk Editorial
Team on 09 January 2008
Low-cost FPGAs secure custom designs
IP core leverages DeviceDNA design security to further streamline and strengthen safeguards against reverse engineering, cloning and unauthorised overbuilding.
Xilinx has worked with data encryption IP specialist Helion Technology to enhance the security features in the Xilinx Spartan-3 generation of low-cost FPGAs The new Helion intellectual property (IP) core leverages Xilinx innovative DeviceDNA design security solution to further streamline and strengthen safeguards against reverse engineering, cloning and unauthorised overbuilding
This article was originally published on Electronicstalk on 18 Apr 2003 at 8.00am (UK)
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"Implementing design safeguards should not be a major time sink for designers".
"With the latest version of our security solution, we provide a robust and flexible approach that can be quickly implemented", says Kevin Kitagawa, Director of High Volume Marketing at Xilinx.
"The additional features added by the Helion IP further strengthen our solution without making it intrusive or requiring compromises in design sise or development time".
Xilinx first introduced its revolutionary DeviceDNA technology, a permanent factory-set ID code that is different in every device, with its low-cost Spartan-3A FPGAs.
Leveraging its proven cryptographic IP and expertise, Helion has developed IP that enables designers to easily implement the Xilinx DeviceDNA technology in their designs.
The Helion approach uses a selection of cryptographic functions to implement the security algorithm and various obfuscation techniques, ensuring that any reverse engineering attacks on the design are made suitably difficult.
Most importantly, the IP is highly parameterised allowing each user to make their implementation unique, thus preventing others using the same IP from working around the security scheme.
"Offering a ready-made and tested IP block that is specifically designed for the Spartan-3 generation streamlines the process of ensuring a highly secure device".
"It also reduces the amount of logic resources typically used for security", says Graeme Durant, CEO for Helion.
"Our solution can be deployed in existing designs very quickly, and now extends the benefits of protection against overbuilding and cloning of products into outsourced manufacturing environments".
Helion's DeviceDNA Checker has relatively low resource requirements and a simple interface, so that it can be easily dropped into the user design alongside the main FPGA application.
The checker uses input from the DeviceDNA block in the FPGA plus other stored values to initiate processing and subsequently generate a "pass/fail" flag.
This flag can be used to degrade normal operation of the rest of the design if the check does not pass.
The DeviceDNA Checker uses the DeviceDNA code, plus additional check bits that are stored in nonvolatile system memory to enhance security.
These bits are a mixed up combination of randomly generated bits that form part of the check algorithm, randomly generated bits that are ignored, and the final stored check code itself.
The additional data are simply streamed into the checker after the DeviceDNA bits.
Pricing for the Helion DeviceDNA solution depends on the exact configuration and security level required, with multi-use site licences starting at US $25,000.
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