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Product category: Design and Development Software
News Release from: XJTAG | Subject: XJTAG 2.0
Edited by the Electronicstalk Editorial Team on 31 October 2007

Development system tracks designs for
testability

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XJTAG 2.0 has a raft of new features, including automated JTAG chain discovery and setup, a built-in netlist explorer, optimised memory test and real-time design for test coverage tracking.

XJTAG has brought out version 2.0 of its popular boundary scan development system, which is reckoned to set a new standard for speed and accuracy of printed circuit board (PCB) debug and test The new version of the XJTAG system - which is used throughout the electronic product life cycle by board developers and manufacturers to debug, test and program complex ball grid array (BGA) populated printed circuit boards and systems - will be unveiled by XJTAG at Productronica (Area A1/Booth 448)

XJTAG 2.0 has a raft of new features, including automated JTAG chain discovery and setup, a built-in netlist explorer, optimised memory test and real-time design for test (DFT) coverage tracking.

It also includes an ever growing library of device-centric test scripts, improved integration with LabView, and support for Xilinx's Virtex-5 FPGA System Monitor.

According to Simon Payne, CEO at XJTAG: "Engineers invariably choose the XJTAG boundary scan system because it's so easy-to-use and because you get everything for debugging and testing complex PCBs in one package for a set price and with no hidden extras".

"While developing the new version, we have listened closely to feedback from our fast-growing base of customers - both design engineers and manufacturers - and have focused on further abstracting engineers from the complexity of the JTAG/IEEE1149.1 standard, in particular, through enhancements to our XJEase programming environment".

With version 2.0, XJTAG has introduced a drag-and-drop interface that automates the JTAG chain discovery and set-up process, thereby saving engineers time and hassle.

The developer simply connects the computer to the unit under test via the USB2.0 XJLink hardware module, creates a new project, and adds the target board.

The XJTAG system then detects the scan chain and matches the JTAG device codes to their respective BSDL files, as well as identifying ground nets and making intelligent suggestions about other components.

In addition, this intelligent set-up facility enables the board developer to quickly and easily categorise all of the nonJTAG or cluster devices in the circuit.

For example, with one click all the pull resistors, or another component type, can be grouped together for speed and convenience during the set-up stage.

XJTAG version 2.0 also includes a built-in netlist explorer that provides a simple interface to view the connectivity between devices on the board.

Other enhancements include an optimised memory test, real-time design for test (DFT) coverage analysis, an extended library of device-centric test scripts, and improved integration with LabView and other leading test executives.

XJTAG has also added support for Xilinx's Virtex-5 FPGA System Monitor to enable customers to check power supplies or perform overall thermal management using the JTAG port on the 65nm Virtex-5 FPGAs.

Dominic Plunkett, Chief Technology Officer at XJTAG, says: "In today's right-first-time environment, engineers need a test solution that not only maximises test coverage but also minimises board debug time".

"Using XJTAG, engineers are able to create valuable test IP, which can be recorded, refined and repeatedly re-used throughout the development cycle".

"With XJTAG v2.0, customers will continue to have an 'all-in-one' boundary scan system that enables them to get their boards up and running in minutes and hours not days and weeks as is the case with some traditional systems".

The XJTAG development system is billed as a cost-effective out-of-the-box solution for debugging, testing and programming electronic printed circuits boards and systems throughout the product lifecycle.

The XJTAG system reduces the time and cost of board development and prototyping by allowing early test development, early design validation of CAD netlists, fast generation of highly functional tests and test re-use across circuits using the same devices.

XJTAG enables engineers to test a high proportion of the circuit (both boundary scan and cluster devices) including BGA and chip scale packages, such as SDRAMs, Ethernet controllers, video interfaces, Flash memories, FPGAs and microprocessors.

XJTAG also enables in-system programming of FPGAs, CPLDs and Flash memories.

The XJTAG system incorporates a number of easy to use software tools.

XJEase is a high-level programming language that provides all the functionality to create a complete JTAG test solution.

XJAnalyser is a powerful tool for circuit visualisation that provides a simple graphical view of the state of all JTAG pins.

XJRunner is a production optimised version of the XJTAG Development System, designed specifically for contract manufacturers and production sites.

The development system also contains the XJLink, which is a USB 2.0 interface used to connect the computer to the unit under test.

The XJLink contains the XJTAG licences.

This enables the system to be used on multiple computers on and off site.

XJDemo is a fully populated demonstrator board, with tutorials designed to provide the developer with a rapid understanding of the XJTAG system.

The XJTAG Professional Development System adds the XJIO board, which improves the test coverage for a unit under test (UUT) by verifying the signals right through to the external connections.

Pricing for the XJTAG system ranges from GBP 3500 (Eur 5075) to GBP 9900 (Eur 14,355).

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