Faster timing closure for cell-based designs

ZenTime 2.1 brings cell-based designers a three- to four-fold increase in run-time speed, allowing them to achieve timing closure on complex, high-speed, nanometre blocks in a matter of days.

ZenTime 2.1 brings cell-based designers a three- to four-fold increase in run-time speed, allowing them to achieve timing closure on complex, high-speed, nanometre blocks up to 600K gates in a matter of days.

ZenTime is the only cell-based timing optimisation product currently able to achieve timing closure for existing nanometre designs that have already been through logic optimisation and physical synthesis.

ZenTime uses a unique hybrid optimisation technology, which helps ASIC and SoC design teams to quickly reach their target performance by injecting design-specific optimised cells into their timing critical designs, resulting in large timing gains into their designs in just the right places.

Using a unique hybrid of transistor, logic, and physical level optimisation, ZenTime can generate timing gains that are two to four times larger than gains achievable using conventional timing closure tools late in the design cycle.

"ASIC designers are facing continuing problems with timing closure for high speed designs.

Mainstream synthesis and optimisation tools are facing difficulty in meeting the timing constraints for 130nm and below processes and for clock rates beyond 300MHz, even using the best optimisation techniques available", noted Dr Rob Roy, VP Marketing and Business Development at Zenasis.

"ZenTime can enable performance gains of 50MHz, or more, making it the only tool capable of closing the large timing shortfalls that are common in nanometre-era designs".

ZenTime improves timing performance in cell-based designs by automatically identifying groups of standard cells in a critical path, and replacing them with custom-crafted design-specific cells, which have been optimised at the transistor level.

The design-specific standard cells created by ZenTime use the same architecture as that employed by a pre-existing standard cell library.

ZenTime can operate as early as in synthesis and as late as in placement stages in a design process, enabling both the front and back end designers to improve performance at critical stages.

Place-and-route tools see no difference between existing standard cells and the design-specific standard cells generated by ZenTime, making the timing optimisation step transparent to the rest of the design process.

The following new features and enhancements are included in the new release: run-time improvement compared with ZenTime 1.2 of three to four times; incremental placement with legalisation; integrated netlist and placement optimisation; support for multiple clock domains; faster incremental timing analysis; support for commonly encountered latch based designs; and improved transistor mapper resulting in improved optimisation quality.

ZenTime 2.1 production version will be available for customers on 30th June 2004.

ZenTime is priced for term based licensing at $195,000 per year.

ZenTime can run on Linux and Sun-Solaris platforms.

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