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Product category: Design and Development Software
News Release from: Zuken | Subject: Cadstar 7.0
Edited by the Electronicstalk Editorial Team on 14 September 2004

Increased accuracy for desktop PCB
design suite

Cadstar 7.0 is a major revision to the long-established scalable, front-to-back desktop PCB design suite.

Cadstar 7.0 is a major revision to the long-established scalable, front-to-back desktop PCB design suite Enhancements include increased routing precision for high-density and miniaturised boards, improved place-and-route automation, definition of lengthening track patterns constraints through a graphical user interface, and a new search tool for finding components and other design items faster

A tool for simulation and verification, Cadstar SI Verify eliminates unnecessary design iterations and is available as an option with the Cadstar 7.0 solution.

Using the upgraded tool suite, placement can now be done with 0.001-degree precision, enabling even the most densely populated boards to be accurately placed and tight design constraints to be set.

This feature is also important for designers of integrated circuit test boards, as test probing points need to be meticulously defined.

The place-and-route editor within the tool suite has additional customisation and scripting options to improve user productivity.

Custom menus can be created, keyboards can be remapped to match the requirements of individual users or host systems, and comprehensive scripting references have been added.

New routing wizards guide users, via a graphical user interface, through step-by-step automated routing routines for complete boards.

Copper pour can now be configured to automatically repour whenever there are changes.

This enables the user to route through copper area, and the copper will be repoured to prevent errors.

Where track lengths need to be adjusted to achieve timing goals, a lengthening wizard has been introduced that allows users to choose their preferred track pattern, via a pull-down menu, for lengthening individual tracks or differential pairs.

Another improvement is the ability to define constraints within component footprints.

If the component is moved, the constrained footprint area automatically moves with it.

Also, the search tool is now faster and easier to use when locating components or other design elements.

Higher performance routers in the PREditor XR 2000 and 5000 families can also be specified as addon options with Cadstar 7.0.

Among other enhancements, constraints can be defined in terms of both length and delay.

In addition, the high-speed versions of the routers enable skew constraints to be set, making it easier to route buses while ensuring that all nets are routed within defined tolerances, preventing timing problems and improving signal integrity control.

The Cadstar SI Verify module provides post-layout simulation and verification.

Operating at up to gigabit speeds, the tool uses a transmission line simulation approach to analyse reflection and crosstalk effects and also facilitates real interconnect timing and delay analysis.

It incorporates a graphical scenario editor, layer stack definition for optimisation of impedances and layers, an EMC device library, and the option to perform interactive simulation or batch simulation.

Using Cadstar SI Verify cuts design iterations, particularly in high-speed and densely populated designs where design "rules-of-thumb" are no longer sufficiently accurate.

Cadstar 7 is available now, and costs from Eur 3650. Request a free brochure from Zuken ...

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