Product category:
Design and Development Software
News Release from: Zuken
Edited by the Electronicstalk Editorial
Team on 24 May 2007
Alliance marries FPGA design and
verification
A new partnership between Zuken and Aldec aims to make it easier for designers to work with programmable devices.
By combining Zuken's expertise in system- and board-level electronics design and verification with Aldec's mixed HDL verification technology, the two companies will be able to offer a combined design and verification flow for flexible field programmable gate array (FPGA) devices on printed circuit boards (PCBs) At this time, the partnership will focus integration efforts on Zuken's enterprise-wide PCB design suite, CR-5000
This article was originally published on Electronicstalk on 23 Sep 2008 at 8.00am (UK)
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The increased density, higher performance and flexibility of FPGA devices has driven a growth in their market share over that of ASICs in recent years.
But the versatility and huge gate count of the latest FPGAs introduces design challenges associated with library management, data sharing, revision control and mixed VHDL, Verilog, SystemC and SystemVerilog simulation; demanding that the complete PCB and FPGA design and verification process be harmonised.
Initial development will allow designers to launch Aldec's mixed language simulation technology from within CR-5000 System Designer for access to project-specific design data.
It will be possible to perform FPGA timing simulation for the complete design rather than for the individual FPGAs in isolation.
Additionally, within CR-5000 Board Designer, layout engineers will be able to perform pin swaps that will concurrently update all PCB and FPGA design data, rather than only be able to perform this on request from the FPGA implementation engineer. Request free introductory details about products from Zuken ...
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