Product category:
Communications ICs (Wired)
News Release from: Zyray Wireless | Subject: Spinnerchip 1.0
Edited by the Electronicstalk Editorial
Team on 24 February 2003
Baseband puts new spin on dual-mode 3G
handsets
The rapid development of dual mode GSM/GPRS and WCDMA handsets is a significant step closer following the introduction of Zyray Wireless' Spinnerchip 1.0 WCDMA baseband processor solution.
The rapid development of dual mode GSM/GPRS and WCDMA handsets is a significant step closer following the introduction of Zyray Wireless' Spinnerchip 1.0 WCDMA baseband processor solution Sampling began ahead of schedule and a complete dual mode WCDMA and GSM/GPRS solution was demonstrated this week at the 3GSM World Congress in Cannes
This article was originally published on Electronicstalk on 26 Feb 2004 at 8.00am (UK)
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Proven to connect to a majority of market-leading GSM/GPRS baseband solutions, Zyray's Spinnerchip 1.0 single chip WCDMA FDD baseband processor began sampling last month.
The solution uses a standard memory interface to connect to existing GSM/GPRS baseband processors.
"As an addon to an existing GSM/GPRS terminal design, Spinnerchip 1.0 provides handset manufacturers with the lowest-risk, lowest-cost path to dual-mode GSM/GPRS and WCDMA handsets", said Werner Sievers, President and CEO of Zyray Wireless.
"This solution is key to reducing a customer's development cycle time, maximizing hardware and software reuse and reducing development costs.
Significant bill of materials savings can also be achieved".
Spinnerchip 1.0 can provide handset manufacturers with a time advantage of up to 12 months and can reduce the cost of a handset development project by as much as $3 million.
By using this dual chip strategy, per handset savings are estimated at between $10 and $20.
Spinnerchip 1.0 is a 3GPP Release 99 March 2002 compliant FDD baseband processor, supporting 384Kbit/s operation in uplink and downlink and integrating all functionality required for WCDMA operation into a single chip.
The chip includes support for WCDMA ciphering, a programmable analog I/Q RF interface, and an optional USIM interface.
Spinnerchip 1.0 includes on-chip programmable power management and proprietary interference cancellation algorithms that provide enhanced bit error rate performance at minimum power consumption.
Currently available in a 16 x 16mm 280-pin LFBGA test package, the chip will be supplied in a 180-pin, 10 x 10mm LFBGA production package.
Spinnerchip 1.0 is supplied with a comprehensive customer development package that includes the Spinner evaluation board.
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