An Electronicstalk guide
Start with the news release PXI module supports JTAG/Boundary Scan Test from Goepel Electronic, which we summarised at the time by saying "At the Defence Systems and Equipment International (DSEI) event, Goepel Electronic launched its PXI 5396/FXT-x, a further series of JTAG/Boundary Scan digital I/O modules on the basis of the PXI bus. ". Several months prior to that, we featured the news release Goepel and SPEA add JTAG/boundary scan functions from Goepel Electronic: "Goepel Electronic and SPEA have introduced additional JTAG/boundary scan functions for the SPEA 4040 Flying Probe tester in the framework of the companies' long-term OEM agreement.".
In October 2008, we covered the news from Goepel Electronic - take a look at Goepel launches PX1 5396-X series which says: "Goepel Electronic has launched a series of JTAG digital I/O PXI modules named PXI 5396-X.".
Take a look also at the news release from Magma Design Automation, Semiconductor device failure analysis improved, as well as Reference design targets UMC 65nm process from Cadence Design Systems, and I/O module at the point of interface testing from Goepel Electronic.
Design upgrade maximises IC throughput (March 2008)
The combination of increasing IC complexity and shrinking semiconductor features is driving increased demand for design and manufacturing-related compute resources.
Partnership provides chip quality boost (February 2008)
The co-operation between Q-Star Test and Source III has already led to the establishment of a push-button automated WGL-based VTRAN flow.
Test generator isolates small delay defects (February 2008)
Higher test quality enables defective parts to be identified earlier in the test process, lowering the cost of production testing.
Scan compression eases HDTV IC test regime (February 2008)
DFT MAX automatically implements scan compression on-chip, which can reduce the amount of data required to test each manufactured part by 95% or more.
Boundary scan is optimised for flying probes (February 2008)
Tools enable an unrivalled level of interaction between flying probe access and boundary scan access for board level test applications, embracing all phases of IEEE1149.1 applications.
Reference design flow eases chip evaluation (November 2007)
Synopsys' Design Compiler Ultra topographical synthesis engine enables engineers to accurately predict chip performance results during logic synthesis.
IC test generator takes power criteria onboard (October 2007)
The TetraMax automatic test pattern generation now creates tests reflecting designers' power budgets.
Test module suits design companies (October 2007)
TetraMAX failure diagnostics data is exported to the new Odyssey DFT module to facilitate comprehensive failure analysis and rapid yield improvement of fabricated devices.
Compression software improves ATPG
TestKompress 2007 is an enhanced version of the ground-breaking tool from Mentor Graphics that introduced scan test pattern compression to the marketplace.
ATPG starter packages improve ASIC quality
The DFT-PRO 100 and 200 Series of automatic test program generator starter packages include the essential design-for-test tools for comprehensive ASIC testing.
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