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Laurence Marchini

Laurence Marchini, Editor, writes:

We see from your search that you're looking for information on the term "EDIF", and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest. Let me be your guide.
Start with the news release Layout tool teaches chip design from EDA Solutions, which we summarised at the time by saying "IC Mask Design uses Tanner's L-Edit layout tool for its training courses". A few weeks before, we featured the news release EDA tool suite features 11 upgrades from EDA Solutions: "Tanner Tools 12.2 is the latest release of the Windows-based EDA tool suite for analogue, mixed-signal and MEMS design from Tanner EDA".
In November 2006, we covered the news from Aldec concerning its System Verification Environment - take a look at Verification environment moves up to Stratix III which says: "Aldec has announced System Verification Environment (SVE) support for Altera Corporation's new high-end Stratix III FPGA device family".
Take a look also at the news release from Synopsys, E-Tools takes interoperability award, as well as Improved C++ Support In SystemC Synthesis Tool from Celoxica, and Kit accelerates programmable SoC development from Celoxica.

See also:

System level design comes to Xilinx FPGAs (March 2006)
The Celoxica ESL Starter Kit provides an out-of-the-box solution for Xilinx FPGA designers who want to pilot and deploy system level design tools and methodologies into their development flows

Environment brings mixed-signal tools together (March 2006)
A new design environment for schematic capture is an integrated suite of affordable Tanner analogue and mixed-signal design capture, simulation, layout, design rule checking and verification tools

Compiler supports latest SystemC standard (January 2006)
The new Agility Compiler for SystemC synthesis can generate RTL descriptions from transaction level models for popular ASIC/SoC synthesis flows and gate-level EDIF netlists for PLDs

Software agreement speeds FPGA design support (December 2005)
A new OEM agreement gives FPGA designers access to a range of performance and productivity benefits using Precision Synthesis within the QuickLogic QuickWorks environment

Timing analysis works with PCB and FPGA flows (November 2005)
Chronology has expanded its TimingDesigner interactive timing analysis and timing diagram product to include tighter integration with vendor-specific board design and FPGA flows