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Product category: Design and Development Software
News Release from: Aldec | Subject: System Verification Environment
Edited by the Electronicstalk Editorial Team on 10 November 2006

Verification environment moves up to
Stratix III

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Aldec has announced System Verification Environment (SVE) support for Altera Corporation's new high-end Stratix III FPGA device family.

Aldec has announced System Verification Environment (SVE) support for Altera Corporation's new high-end Stratix III FPGA device family SVE supports all aspects of system-level design development and verification

It includes an industry-leading common kernel HDL simulator, a set of online