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Product category: Design and Development Software
News Release from: Celoxica | Subject: Agility Compiler
Edited by the Electronicstalk Editorial Team on 17 January 2006

Compiler supports latest SystemC
standard

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The new Agility Compiler for SystemC synthesis can generate RTL descriptions from transaction level models for popular ASIC/SoC synthesis flows and gate-level EDIF netlists for PLDs.

Celoxica has announced the latest release of its Agility Compiler for SystemC synthesis supporting SystemC prototyping and verification The new release can generate RTL descriptions from transaction level models (TLM) for popular ASIC/SoC synthesis flows and gate-level EDIF netlists for programmable logic devices