Interra nibbles Elixent
into SoC design flow
Elixent has enlisted the help of Interra Technologies to develop tools that allow the easy integration of its reconfigurable arithmetic logic unit (ALU) array into a standard chip design flow
The first results of the partnership between Elixent and Interra, which was established in 2001, are expected in the second quarter of 2002. The companies are working on design software based on Interra's synthesis tool, Concorde, that will map designs written in Verilog onto Elixent's reconfigurable array.
It will use a customised version of the Concorde software and output a bitstream to configure the ALU array once the silicon has been fabricated.
By developing a tool optimised to the 4bit architecture of the array, very efficient configurations can be produced which minimise the size of the array required and therefore the silicon area.
This development means that SoC designers will continue to use existing design flow tools and simply plug-in an additional tool to efficiently incorporate an Elixent reconfigurable ALU array.
The tool is a customised version of Interra's embedded RTL synthesis tool developed specifically for Elixent.
"This is a very important development that means designers will be able to incorporate Elixent's RSP technology into the normal design flow.
There will be no need for the designer to learn anything new or change the way that they currently do their designs", commented Kenn Lamb, CEO at Elixent.
"A customised tool design based on the 4it nibble architecture of the array is the optimal design method.
The alternative approach of supplying a library of functions to a standard design tool would have been much less efficient and resulted in larger arrays, larger chips and more expense".
"Our existing Concorde synthesis tool is an ideal starting point to extend to 4-bit arrays such as Elixent's", said Sunil Jain, CEO at Interra.
"The partnership is running very well and we expect tangible results within the next quarter".
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